24FC32 Datasheet, PDF (6/12 Pages) Microchip Technology – 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM

24FC32
4.0 WRITE OPERATION
4.1 Split Endurance
The 24FC32 is organized as a continuous 32K block of
memory. However, the first 4K, starting at address 000,
is rated at 10,000,000 E/W cycles guaranteed. The
remainder of the array, 28K bits, is rated at 100K E/W
cycles guaranteed. This feature is helpful in
applications in which some data change frequently,
while a majority of the data change infrequently. One
example would be a cellular telephone in which
last-number redial and microcontroller scratch pad
require a high-endurance block, while speed dials and
lookup tables change infrequently and so require only a
standard endurance rating.
4.2 Byte Write
Following the start condition from the master, the
control code (four bits), the device select (three bits),
and the R/W bit which is a logic low are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore
the next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24FC32. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24FC32 the master
device will transmit the data word to be written into the
addressed memory location. The 24FC32 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24FC32 will not generate acknowledge
signals (Figure 4-1).
4.3 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC32 in the same way as
in a byte write. But instead of generating a stop
condition, the master transmits up to eight pages of
eight data bytes each (64 bytes total) which are
temporarily stored in the on-chip page cache of the
24FC32. They will be written from cache into the
EEPROM array after the master has transmitted a stop
condition. After the receipt of each word, the six lower
order address pointer bits are internally incremented by
one. The higher order seven bits of the word address
remain constant. If the master should transmit more
than eight bytes prior to generating the stop condition
(writing across a page boundary), the address counter
(lower three bits) will roll over and the pointer will be
incremented to point to the next line in the cache. This
can continue to occur up to eight times or until the
cache is full, at which time a stop condition should be
generated by the master. If a stop condition is not
received, the cache pointer will roll over to the first line
(byte 0) of the cache, and any further data received will
overwrite previously captured data. The stop condition
can be sent at any time during the transfer. As with the
byte write operation, once a stop condition is received,
an internal write cycle will begin. The 64-byte cache will
continue to capture data until a stop condition occurs or
the operation is aborted (Figure 4-2).
FIGURE 4-1: BYTE WRITE
BUS ACTIVITY:
MASTER
S
T CONTROL
A
BYTE
R
T
WORD
ADDRESS (1)
WORD
ADDRESS (0)
S
T
DATA
O
P
SDA LINE
0000
BUS ACTIVITY
A
A
A
A
C
C
C
C
K
K
K
K
FIGURE 4_S-2:
T
BUS
A
ACTIVITY _R
MASTER _T
PAGE WRITE
CONTROL
BYTE
WORD
ADDRESS (1)
WORD
ADDRESS (0)
DATA n
S
DATA n+7
T
O
P
SDA LINE
0000
BUS
ACTIVITY
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
DS21126B-page 3-6
© 1996 Microchip Technology Inc.