24C01B_04 Datasheet, PDF (7/10 Pages) Microchip Technology – 1K/2K 5.0V I2C™ Serial EEPROM

24C01B/02B
FIGURE 7-1: CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
T
A
R
T
CONTROL
BYTE
SDA LINE
S
BUS ACTIVITY
A
C
K
DATA n
FIGURE 7-2: RANDOM READ
S
BUS ACTIVITY
T
A
MASTER
R
T
CONTROL
BYTE
SDA LINE
S
BUS ACTIVITY
S
WORD
ADDRESS (n)
T
A
R
T
S
A
A
C
C
K
K
CONTROL
BYTE
A
C
K
S
T
O
P
P
N
O
A
C
K
S
T
DATA n
O
P
P
N
O
A
C
K
FIGURE 7-3: SEQUENTIAL READ
BUS ACTIVITY CONTROL
MASTER
BYTE
SDA LINE
A
BUS ACTIVITY
C
K
DATA n
A
A
A
C
C
C
K
K
K
DATA n + 1
DATA n + 2
S
T
O
P
P
N
DATA n + X ^O
A
C
K
8.0 PIN DESCRIPTIONS
8.1 Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typically 10 K¾ for 100 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24C01B/02B as
a serial ROM when WP is enabled (tied to VCC).
 2004 Microchip Technology Inc.
Preliminary
DS21233B-page 7