24C01B_04 Datasheet, PDF (4/10 Pages) Microchip Technology – 1K/2K 5.0V I2C™ Serial EEPROM

24C01B/02B
2.0 FUNCTIONAL DESCRIPTION
The 24C01B/02B supports a bi-directional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C01B/02B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B)
(D)
(D)
SCL
(C) (A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
DS21233B-page 4
Preliminary
 2004 Microchip Technology Inc.