PIC16C781 Datasheet, PDF (69/186 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC

PIC16C781/782
Example 8-1 shows the configuration of the PLVD mod-
ule and a sample polling routine to monitor for low volt-
age conditions.
EXAMPLE 8-1: PLVD EXAMPLE
;************************************************
;* This code block will configure the PLVD for polling
;* and set the trip point for 4.2 to 4.4 volts
;* Includes polling routine
;*
BANKSEL
BCF
MOVLW
MOVWF
LVDCON
PIE1,LVDIE
B’00011101’
LVDCON
; Select Bank 1
; Disable PLVD interrupt
; Enable PLVD, 4.2-4.4V trip
WRM_UP
BTFSS
GOTO
BANKSEL
BCF
LVDCON,BGST
WRM_UP
PIR1
PIR1,LVDIF
;
;
; Select Bank 0
; Clear PLVD interrupt flag
;**************************************************
;* Test for PLVD trip
BANKSEL
BTFSC
GOTO
PIR1
PIR1,LVDIF
LO_V_DET
; Select Bank 0
; Test for PLVD trip
; If tripped save 4 pwrfail
8.3 Operation During SLEEP
When enabled, the PLVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit is set and the device awakens from
SLEEP. Device execution continues from the interrupt
vector address, if interrupts have been globally
enabled.
8.4 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the PLVD module to be disabled.
8.5 Low Voltage Detect Registers
The registers associated with Programmable Low Volt-
age Detect are shown in Table 8-1.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH LOW VOLTAGE DETECT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
09Ch
08Ch
08Ch
LVDCON —
— BGST LVDEN LV3
PIE1
LVDIE ADIE C2IE C2IE
—
PIR1
LVDIF ADIF C2IF C2IF
—
Bit 2
LV2
—
—
Bit 1
LV1
—
—
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
LV0
TMR1IE
TMR1IF
--00 0101
0000 ---0
0000 ---0
--00 0101
0000 ---0
0000 ---0
 2001 Microchip Technology Inc.
Preliminary
DS41171A-page 67