DSPIC30F3010-30I Datasheet, PDF (68/226 Pages) Microchip Technology – dsPIC30F3010/3011 Data Sheet

dsPIC30F3010/3011
FIGURE 9-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
PR1
Equal
Comparator x 16
Reset
0
T1IF
Event Flag
1
TGATE
TMR1
QD
Q CK
SOSCO/
T1CK
SOSCI
LPOSCEN
Gate
Sync
TCY
TGATE
TSYNC
1
Sync
0
TON
1X
01
00
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
9.1 Timer Gate Operation
The 16-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal TCY
to increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit, TGATE
(T1CON<6>), must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2 Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
9.3 Timer Operation During Sleep
Mode
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 1) and
• The TSYNC bit (T1CON<2>) is asserted to a logic
‘0’, which defines the external clock source as
asynchronous
When all three conditions are true, the timer will
continue to count up to the Period register and be reset
to 0x0000.
When a match between the timer and the Period
register occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.
DS70141E-page 66
© 2008 Microchip Technology Inc.