24AA174 Datasheet, PDF (6/12 Pages) Microchip Technology – 16K 1.8V Cascadable I2C™ Serial EEPROM with OTP Security Page

24AA174
FIGURE 4-1: BYTE WRITE
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
CONTROL
R
BYTE
T
S 1 A2 A1 A0 B2 B1 B0
WORD
ADDRESS
S
T
DATA
O
P
P
BUS ACTIVITY:
A
A
A
C
C
C
K
K
K
FIGURE 4-2: PAGE WRITE
S
T
BUS ACTIVITY: A
MASTER
R
T
CONTROL
BYTE
SDA LINE
S A2 A1 A0 B2 B1 B0
WORD
ADDRESS (n)
BUS ACTIVITY:
A
A
C
C
K
K
DATA n
DATA n + 1
A
A
C
C
K
K
S
T
DATA n + 15 O
P
P
A
C
K
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
NO
(ACK = 0)?
YES
Next
Operation
6.0 WRITE PROTECTION
The 24AA174 can be used as a serial ROM when the
WP pin is connected to VCC. Programming will be inhib-
ited and the entire memory will be write-protected.
DS21102G-page 6
 2004 Microchip Technology Inc.