24AA174 Datasheet, PDF (5/12 Pages) Microchip Technology – 16K 1.8V Cascadable I2C™ Serial EEPROM with OTP Security Page

3.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA174 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24AA174 will select a read
or write operation.
Operation Control Code Block Select R/W
Read
Write
1 A2 A1 A0 Block Address 1
1 A2 A1 A0 Block Address 0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1 A2 A1 A0 B2 B1 B0
MSB
LSB
24AA174
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24AA174. After
receiving another acknowledge signal from the
24AA174 the master device will transmit the data word
to be written into the addressed memory location. The
24AA174 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24AA174 will not gener-
ate acknowledge signals (see Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA174 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to 16 data bytes to the
24AA174 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 4-2).
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples
of the page buffer size (or ‘page size’) and
end at addresses that are integer multiples
of [page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
 2004 Microchip Technology Inc.
DS21102G-page 5