MCP37231 Datasheet, PDF (59/144 Pages) Microchip Technology – Power-Saving Modes

MCP37231/21-200 AND MCP37D31/21-200
4.8.3.2 Dual-Channel DDC
Figure 4-17 shows the dual-channel DDC configura-
tion. Each channel includes the same processing ele-
ments as shown in the single-channel DDC, however
the I/Q outputs cannot be separately decimated since
the device only supports two channels of decimation
(four would be required for I/Q of Channel A and I/Q of
Channel B). The decimation option can be used if the
DDC output after the half-band filter is up-converted by
f_S/8 for each channel. Otherwise, I/Q of each channel
will be output separately, similar to a four-channel input
device with the WCK output pin toggling synchronously
with the I-data of Channel A. Note that the NCO phase
can be adjusted uniquely for each of the two input
channels (see Figure 4-18). Examples of setting regis-
ters for selected output type are shown in Tables 4-16
and 4-17.
ADC
Data:
CH. A
(Note 3)
I_A
Half-Band Filter A
Q_A
LP/HP
CH. B
COS
SIN
NCO (32-bit)
(Note 2)
COS
SIN
HBFILTER_A
EN_NCO
EN_DDC_F_S/8
EN_DDC2
(Note 3)
Q_B
Half-Band Filter B
I_B
LP/HP
NCO (f_S/8)
I_A
Q_A
Real_A
Real_B
EN_DDC1
HBFILTER_B
I_B
Q_B
Down-Converting and Decimation (Note 1) Output Frequency Translation and Decimation (Note 1)
Note 1: See Address 0x80 – 0x81 for the Control Parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A and B include a single-stage decimation filter.
FIGURE 4-17:
Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-16 and 4-17 for
Using this DDC Block.
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DS20005322D-page 59