MCP37231 Datasheet, PDF (53/144 Pages) Microchip Technology – Power-Saving Modes

MCP37231/21-200 AND MCP37D31/21-200
4.8 Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the Configuration bits. Table 4-9
summarizes the digital signal post-processing (DSPP)
options that are available for each device family.
TABLE 4-9: DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS
Digital Signal Post Processing Option
Available Operating Mode
Fractional Delay Recovery (FDR)
FIR Decimation Filters
Dual and octal-channel modes
Single and dual-channel modes
CW octal-channel mode
DDC for I and Q data
Digital Gain and Offset correction per channel Available for all channels
Digital-Down Conversion (DDC)
Single and dual-channel modes
Continuous Wave (CW) Beamforming
CW octal-channel mode
CW octal-channel mode
Offering Device
MCP37231/21-200
MCP37D31/21-200
MCP37D31/21-200
4.8.1
FRACTIONAL DELAY RECOVERY
FOR DUAL- AND OCTAL-CHANNEL
MODES
The FDR feature is available in dual and octal-channel
modes only. When FDR is enabled, the built-in high-
order, band-limited interpolation filter compensates for
the time delay between input samples of different
channels. Due to the finite bandwidth of the
interpolation filter, the fractional delay recovery is not
guaranteed for input frequencies near the Nyquist
frequency (f_S/2). For example, in dual-channel mode,
FDR can operate correctly for input frequencies in the
range from 0 to 0.45*f_S (or from 0.55*fs to f_S if the input
is in the 2nd Nyquist band). In octal-channel mode,
FDR can operate correctly for input frequencies in the
range from 0 to 0.38*f_S. See Table 4-11 for the
summary of the input bandwidth requirement for FDR.
The FDR process takes place in the digital domain and
requires 59 clock cycles of processing time. Therefore,
the output data latency is also increased by 59 clock
periods.
Figure 4-12 shows the simplified block diagram for the
ADC output data path with FDR. The related
Configuration register bits are listed in Table 4-10.
Table 4-11 shows the input bandwidth limits of the FDR
feature for distortion less than 0.1 mdB (0.1 × 10^-3 dB),
where f_S is the sampling frequency per channel.
Figures 4-13 and 4-14 show the responses of the dual-
channel and octal-channel FDRs, respectively.
ADC Output for
dual- or octal-channel
Fractional Delay
Recovery
(FDR)
FIR
Decimation Filters
Digital
Down-Conversion (DDC)
(MCP37D31/21-200)
FDR Control
CW
Beamforming
(MCP37D31/21-200)
ADC data after
sampling time delay between
channels is removed
FIGURE 4-12:
Simplified Block Diagram for
ADC Output Data Path with Fractional Delay
Recovery Option. Note that Fractional Delay
Recovery occurs prior to other DSPP features.
 2014-2016 Microchip Technology Inc.
DS20005322D-page 53