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PIC16LF76-I Datasheet, PDF (577/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers | |||
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PIC18F66K80 FAMILY
TABLE 31-22: MSSP I2C⢠BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High
100 kHz mode 2(TOSC)(BRG + 1) â
â
Time
400 kHz mode 2(TOSC)(BRG + 1) â
â
1 MHz mode(1) 2(TOSC)(BRG + 1) â
â
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) â
â
400 kHz mode 2(TOSC)(BRG + 1) â
â
1 MHz mode(1) 2(TOSC)(BRG + 1) â
â
102 TR
SDA and SCL 100 kHz mode
Rise Time
400 kHz mode
â
20 + 0.1 CB
1000
300
ns CB is specified to be from
ns 10 to 400 pF
1 MHz mode(1)
â
300 ns
103 TF
SDA and SCL 100 kHz mode
Fall Time
400 kHz mode
â
20 + 0.1 CB
300 ns CB is specified to be from
300 ns 10 to 400 pF
1 MHz mode(1)
â
100 ns
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â
â Only relevant for Repeated
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â
â Start condition
1 MHz mode(1) 2(TOSC)(BRG + 1) â
â
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â
â After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) â
â clock pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) â
â
106 THD:DAT Data Input
100 kHz mode
0
Hold Time
400 kHz mode
0
â
â
0.9 ïs
1 MHz mode(1)
â
ïs
ns
107 TSU:DAT Data Input
100 kHz mode
250
Setup Time
400 kHz mode
100
â
ns (Note 2)
â
ns
1 MHz mode(1)
â
â
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) â
â
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â
â
1 MHz mode(1) 2(TOSC)(BRG + 1) â
â
109 TAA
Output Valid 100 kHz mode
â
3500 ns
from Clock
400 kHz mode
â
1000 ns
1 MHz mode(1)
â
â
ns
110 TBUF Bus Free Time 100 kHz mode
4.7
400 kHz mode
1.3
1 MHz mode(1)
â
â
ïs Time the bus must be free
â
ïs before a new transmission
â
ïs can start
D102 CB
Bus Capacitive Loading
â
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C⢠pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107 ï³ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line, Parameter #102 + Parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL
line is released.
ï£ 2010-2012 Microchip Technology Inc.
DS39977F-page 577
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