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PIC16LF76-I Datasheet, PDF (489/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers | |||
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PIC18F66K80 FAMILY
29.1.1 STANDARD INSTRUCTION SET
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
ADD Literal to W
ADDLW k
0 ï£ k ï£ 255
(W) + k ï® W
N, OV, C, DC, Z
0000 1111 kkkk kkkk
The contents of W are added to the
8-bit literal âkâ and the result is placed in
W.
1
1
Q2
Read
literal âkâ
Q3
Process
Data
Q4
Write to
W
Example:
ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
ADD W to f
ADDWF f {,d {,a}}
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
(W) + (f) ï® dest
N, OV, C, DC, Z
0010 01da ffff ffff
Add W to register âfâ. If âdâ is â0â, the
result is stored in W. If âdâ is â1â, the
result is stored back in register âfâ
(default).
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 29.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG =
After Instruction
W
=
REG =
17h
0C2h
0D9h
0C2h
REG, 0, 0
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
ï£ 2010-2012 Microchip Technology Inc.
DS39977F-page 489
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