KSZ8895MQX Datasheet, PDF (55/108 Pages) Microchip Technology – Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface

KSZ8895MQX/RQX/FQX/MLX
TABLE 4-3: PORT REGISTERS (CONTINUED)
Address Name
Description
This bit 0 in the Register16/32/48/64/80 should be
in combination with Register177/193/209/225/241
bit 1 for Port 1-5 will select the split of 1/2/4
queues:
For Port 1, [Register 177 bit 1, Register 16 bit 0] =
0
Two Queues
Split Enable
[11], Reserved
[10], the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
[01], the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
[00], single output queue on the port. There is no
priority differentiation even though packets are
classified into high or low priority.
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Register 65 (0x41): Port 4 Control 1
Register 81 (0x51): Port 5 Control 1
1, port is designated as sniffer port and will transmit
7
Sniffer Port packets that are monitored.
0, port is a normal port.
1, all the packets received on the port will be
6
Receive Sniff
marked as “monitored packets” and forwarded to
the designated “sniffer port.”
0, no receive monitoring.
1, all the packets transmitted on the port will be
5
Transmit
Sniff
marked as “monitored packets” and forwarded to
the designated “sniffer port.”
0, no transmit monitoring.
4-0
Port VLAN
Membership
Define the port’s Port VLAN membership. Bit 4
stands for Port 5, bit 3 for Port 4...bit 0 for Port 1.
The port can only communicate within the member-
ship. A ‘1’ includes a port in the membership, a ‘0’
excludes a port from membership.
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Register 66 (0x42): Port 4 Control 2
Register 82 (0x52): Port 5 Control 2
1, If packet’s “user priority field” is greater than the
“user priority field” in the port default tag register,
replace the packet’s “user priority field” with the
7
User Priority “user priority field” in the port default tag Register
Ceiling
control 3.
0, no replacement of packet’s priority filed with port
default tag priority filed of the Register Port Control
3 bit [7:5].
6
Ingress
VLAN
Filtering.
1, the switch will discard packets whose VID port
membership in VLAN table bit [11:7] does not
include the ingress port.
0, no ingress VLAN filtering.
5
Discard Non-
PVID packets
1, the switch will discard packets whose VID does
not match ingress port default VID.
0, no packets will be discarded.
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0x1f
0
0
0
 2016 Microchip Technology Inc.
DS00002246A-page 55