KSZ8061MNX Datasheet, PDF (54/64 Pages) Microchip Technology – 10BASE-T/100 BASE-TX Physical Layer Transceiver

KSZ8061MNX/MNG
FIGURE 7-7:
POWER-UP/RESET TIMING
The KSZ8061MN reset timing requirement is summarized in Figure 7-7 above and Table 7-7 below.
TABLE 7-7: POWER-UP/RESET TIMING PARAMETERS
Timing
Parameter
Description
Min. Typ. Max. Units
t_VR
Supply voltage (VDDIO, AVDD, VDDL, AVDDL) rise time
300
—
—
µs
t_SR
Stable supply voltage (VDDIO, AVDD, VDDL, AVDDL) to
10
—
—
ms
reset high
t_CS
Configuration setup time
t_CH
Configuration hold time
t_RC
Reset to strap-in pin output
5
—
—
5
—
—
ns
6
—
—
The supply voltage (VDDIO, AVDD, VDDL, AVDDL) power-up waveforms should be monotonic, and the 300 µs mini-
mum rise time is from 10% to 90%.
For warm reset, the reset (RESET#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are
read and updated at the de-assertion of reset.
After the de-assertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM
(MDC/MDIO) Interface.
DS00002038A-page 54
 2016 Microchip Technology Inc.