MCP45HVX1 Datasheet, PDF (51/100 Pages) Microchip Technology – Single-Resistor Network

6.2.4 ADDRESSING
The address byte is the first byte received following the
Start condition from the master device. The address
contains four (or more) fixed bits and (up to) three user-
defined hardware address bits (pins A1 and A0). These
7-bits address the desired I²C device. The A6:A2
address bits are fixed to ‘01111’ and the device
appends the value of following two address pins (A1
and A0).
Since there are address bits controlled by hardware
pins, there may be up to four MCP45HVX1 devices on
the same I²C bus.
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write (R/W) bit. Table 6-2 shows the fixed address for
device.
Hardware Address Pins
The hardware address bits (A1, and A0) correspond to
the logic level on the associated address pins. This
allows up to four devices on the bus.
MCP45HVX1
Slave Address
S A6 A5 A4 A3 A2 A1 A0 R/W _A/A
“0” “1” “1” “1” “1”
See Table 6-2
Start
bit
R/W bit
R/W = 0 = write
R/W = 1 = read
A bit (controlled by slave device)
A = 0 = Slave device Acknowledges byte
A = 1 = Slave device does not Acknowledge byte
FIGURE 6-9:
Slave Address Bits in the
I²C Control Byte.
TABLE 6-2: DEVICE SLAVE ADDRESSES
Device
Address
Comment
MCP45HVX1 ‘0111 1’b + A1:A0 Supports up to
4 devices.
Note 1:
(Note 1)
The fixed portion of the I²C address is dif-
ferent than the MCP44XX/MCP45XX/
MCP46XX family (‘0101 11’, ‘0101 1’,
or ‘0101’). This allows the maximum num-
ber of both standard and high-voltage
devices on the single I²C bus.
6.2.5 SLOPE CONTROL
The MCP45HVX1 implements slope control on the
SDA output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmitt trigger at SDA
and SCL inputs.
 2014 Microchip Technology Inc.
DS20005304A-page 51