TC1275_07 Datasheet, PDF (5/12 Pages) Microchip Technology – 3-Pin Reset Monitors for 3.3V Systems

TC1275/TC1276/TC1277
3.2 V_CC Transient Rejection
The TC1275/TC1276/TC1277 provides accurate V_CC
monitoring and reset timing during power-up, power-
down, and brownout/sag conditions, and rejects
negative-going transients (glitches) on the power
supply line. Figure 3-5 shows the maximum transient
duration vs. maximum negative excursion (overdrive)
for glitch rejection. Any combination of duration and
overdrive that lays under the curve will not generate a
reset signal. Combinations above the curve are
detected as a brownout or power-down. Transient
immunity can be improved by adding a capacitor in
close proximity to the V_CC pin of the TC1275/TC1276/
TC1277.
3.3 RESET Signal Integrity During
Power-Down
The TC1275 RESET output is valid to V_CC = 1.2V.
Below this voltage the output becomes an "open
circuit" and does not sink current. This means CMOS
logic inputs to the μP will be floating at an undeter-
mined voltage. Most digital systems are completely
shut down well above this voltage. However, in situa-
tions where RESET must be maintained valid to
V_CC = 0V, a pull-down resistor must be connected from
RESET to ground to discharge stray capacitances and
hold the output low (Figure 3-6). This resistor value,
though not critical, should be chosen such that it does
not appreciably load RESET under normal operation
(100 kΩ will be suitable for most applications). Simi-
larly, a pull-up resistor to V_CC is required for the
TC1277 to ensure a valid high RESET for V_CC below
1.8V.
V_CC
V_TH
Overdrive
Duration
500
T_A
°C
400
300
200
100
TC1275/6/7
0
1
10
100
1000
RESET COMPARATOR OVERDRIVE,
[V_CCTP - V_CC] (mV)
FIGURE 3-5:
Maximum Transient
Duration Vs. Overdrive For Glitch Rejection At
+25°C.
V_CC
V_CC
TC1275
RESET
GND
R1
100k
FIGURE 3-6:
TO V_CC = 0V.
ENSURING RESET VALID
© 2007 Microchip Technology Inc.
DS21383C-page 5