TC1047_06 Datasheet, PDF (5/12 Pages) Microchip Technology – High Current Charge Pump DC-to-DC Converter

TC962
3.0 APPLICATIONS INFORMATION
3.1 Theory of Operation
The TC962 is a capacitive pump (sometimes called a
switched capacitor circuit), where four MOSFET
switches control the charge and discharge of a
capacitor.
The functional block diagram shows how the switching
action works. SW1 and SW2 are turned on simulta-
neously, charging C_P to the supply voltage, V_IN. This
assumes that the on resistance of the MOSFETs in
series with the capacitor results in a charging time
(3 time constants) that is less than the on time provided
by the oscillator frequency as shown:
3 (R_DS(ON) C_P) < C_P/(0.5 f_OSC)
In the next cycle, SW1 and SW2 are turned off and after
a very short interval of all switches being off (this
prevents large currents from occurring due to cross
conduction), SW3 and SW4 are turned on. The charge
in C_P is then transferred to C_R, but with the polarity
inverted. In this way, a negative voltage is now derived.
An oscillator supplies pulses to a flip-flop that is then
fed to a set of level shifters. These level shifters then
drive each set of switches at one-half the oscillator
frequency.
The oscillator has two pins that control the frequency of
oscillation. Pin 7 can have a capacitor added that is
returned to ground. This will lower the frequency of the
oscillator by adding capacitance to the timing capacitor
internal to the TC962. Grounding pin 6 will turn on a
current source and double the frequency. This will
double the charge current going into the internal
capacitor, as well as any capacitor added to pin 7.
A Zener diode has been added to the TC962 for use as
a reference in building external regulators. This Zener
runs from pin 1 to ground.
3.2 Latch-Up
All CMOS structures contain a parasitic SCR. Care
must be taken to prevent any input from going above or
below the supply rail, or latch-up will occur. The result
of latch-up is an effective short between V_DD and V_SS.
Unless the power supply input has a current limit, this
latch-up phenomena will result in damage to the
device. (See AN763, Latch-up Protection for MOSFET
Drivers.)
690
NC
1
8
2
7
+ 10 μF
C_P
3
TC962
4
5
C_OSC
I_{S V +}
I_L ^(+5V)
R_L
V_OUT
(–5V)
C_{R +} 10 μF
FIGURE 3-1:
Test Circuit
Combined Negative Converter and Positive Multiplier
V+
1
2
C_P2 ^{+ 10 μF} 3
4
TC962
C_P1
+
8
7
6
5 ^{VOUT = –V+}
+ ^{10 μF}
V_D1
V_D2
+
C_R1
V_OUT =
2V+ –2V_D
10 μF
Split V+ In Half
V+
1
8
2
7
+ 10 μF
C_P
3 _TC962 6
4
5
C_R ⁺
V_OUT
=
V+
2
10 μF
Lowering Output Resistance by Paralleling Devices
V+
1
8
2
7
+
C_P1
10 μF3
TC962
6
4
5
1
8
2
7
+
C_P2
10 μF ₃
TC962
6
4
5
C_R
+
V_OUT
10 μF
Positive Voltage Multiplier
V+
1
8
2
7
3 ^TC962 6
4
5
V_D1
V_D2
C_P
+
10 μF +
C_P
V_OUT =
2V ^+–2V_D
10 μF
FIGURE 3-2:
Typical Applications
© 2006 Microchip Technology Inc.
DS21484C-page 5