TC1027 Datasheet, PDF (5/18 Pages) TelCom Semiconductor, Inc – LINEAR BUILDING BLOCK - QUAD LOW POWER COMPARATOR AND VOLTAGE REFERENCE

4.2 Precision Battery Monitor
Figure 4-2 is a precision battery low/battery dead
monitoring circuit. Typically, the battery low output
warns the user that a battery dead condition is
imminent. Battery dead typically initiates a forced
shutdown to prevent operation at low internal supply
voltages (which can cause unstable system operation).
The circuit of Figure 4-2 uses a single TC1027, one
additional op amp, and only six external resistors.
AMP 1 is a simple buffer while CMPTR1 and CMPTR2
provide precision voltage detection using V_R as a
reference. Resistors R2 and R4 set the detection
threshold for BATT LOW while resistors R1 and R3 set
the detection threshold for BATT FAIL. The component
values shown assert BATT LOW at 2.2V (typical) and
BATT FAIL at 2.0V (typical). Total current consumed by
this circuit is typically 24µA at 3V. Resistors R5 and R6
provide hysteresis for comparators CMPTR1 and
CMPTR2, respectively.
4.3 32.768 kHz “Time of Day Clock”
Crystal Controlled Oscillator
A very stable oscillator driver can be designed by using
a crystal resonator as the feedback element. Figure 4-3
shows a typical application circuit using this technique
to develop clock driver for a Time Of Day (TOD) clock
chip. The value of R_A and R_B determine the DC voltage
level at which the comparator trips – in this case one-
half of V_DD. The RC time constant of R_C and C_A should
be set several times greater than the crystal oscillator’s
period, which will ensure a 50% duty cycle by maintain-
ing a DC voltage at the inverting comparator input
equal to the absolute average age of the output signal.
4.4 Non-Retriggerable One Shot
Multivibrator
Using two comparators, a non-retriggerable one shot
multivibrator can be designed using the circuit configu-
ration of Figure 4-4. A key feature of this design is that
the pulse width is independent of the magnitude of the
supply voltage because the charging voltage and the
intercept voltage are a fixed percentage of V_DD. In
addition, this one shot is capable of pulse width with as
much as a 99% duty cycle and exhibits input lockout to
ensure that the circuit will not retrigger before the
output pulse has completely timed out. The trigger level
is the voltage required at the input to raise the voltage
at node A higher than the voltage at node B, and is set
by the resistive divider R4 and R10 and the impedance
network composed of R1, R2 and R3. When the one
shot has been triggered, the output of CMPTR2 is high,
causing the reference voltage at the non-inverting input
of CMPTR1 to go to V_DD. This prevents any additional
input pulses from disturbing the circuit until the output
pulse has timed out.
TC1027
The value of the timing capacitor C1 must be small
enough to allow CMPTR1 to discharge C1 to a diode
voltage before the feedback signal from CMPTR2
(through R10) switches CMPTR1 to its high state and
allows C1 to start an exponential charge through R5.
Proper circuit action depends upon rapidly discharging
C1 through the voltage set by R6, R9 and D2 to a final
voltage of a small diode drop. Two propagation delays
after the voltage on C1 drops below the level on the
non-inverting input of CMPTR2, the output of CMPTR1
switches to the positive rail and begins to charge C1
through R5. The time delay which sets the output pulse
width results from C1 charging to the reference voltage
set by R6, R9 and D2, plus four comparator propaga-
tion delays. When the voltage across C1 charges
beyond the reference, the output pulse returns to
ground and the input is again ready to accept a trigger
signal.
4.5 Oscillators and Pulse Width
Modulators
Microchip’s linear building block comparators adapt
well to oscillator applications for low frequencies (less
than 100kHz). Figure 4-5 shows a symmetrical square
wave generator using a minimum number of compo-
nents. The output is set by the RC time constant of R4
and C1, and the total hysteresis of the loop is set by R1,
R2 and R3. The maximum frequency of the oscillator is
limited only by the large signal propagation delay of the
comparator in addition to any capacitive loading at the
output which degrades the slew rate. To analyze this
circuit, assume that the output is initially high. For this
to occur, the voltage at the inverting input must be less
than the voltage at the non-inverting input. Therefore,
capacitor C1 is discharged. The voltage at the
non-inverting input (V_H) is:
EQUATION 4-5:
V_H = _[---_R----₂----^R-+----²-₍--⁽-_R--^V--₁--^D---_|-^D_|---_R-⁾----₃----₎--_]-
where, if R1 = R2 = R3, then:
EQUATION 4-6:
V_H
=
2----(_{---V----D---D----})_-
3
© 2002 Microchip Technology Inc.
DS21284B-page 5