TC1025 Datasheet, PDF(5/16 Page) TelCom Semiconductor, Inc – LINEAR BUILDING BLOCK

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TC1025 Datasheet, PDF (5/16 Pages) TelCom Semiconductor, Inc – LINEAR BUILDING BLOCK - DUAL LOW POWER COMPARATOR

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4.2 32.768 kHz âTime of Day Clockâ

Crystal Controlled Oscillator

A very stable oscillator driver can be designed by using

a crystal resonator as the feedback element. Figure 4-2

shows a typical application circuit using this technique

to develop clock driver for a Time Of Day (TOD) clock

chip. The value of RA and RB determine the DC voltage

level at which the comparator trips â in this case one-

half of VDD. The RC time constant of RC and CA should

be set several times greater than the crystal oscillatorâs

period, which will ensure a 50% duty cycle by maintain-

ing a DC voltage at the inverting comparator input

equal to the absolute average age of the output signal.

4.3 Non-Retriggerable One Shot

Multivibrator

Using two comparators, a non-retriggerable one shot

multivibrator can be designed using the circuit configu-

ration of Figure 4-3. A key feature of this design is that

the pulse width is independent of the magnitude of the

supply voltage because the charging voltage and the

intercept voltage are a fixed percentage of VDD. In

addition, this one shot is capable of pulse width with as

much as a 99% duty cycle and exhibits input lockout to

ensure that the circuit will not retrigger before the

output pulse has completely timed out. The trigger level

is the voltage required at the input to raise the voltage

at node A higher than the voltage at node B, and is set

by the resistive divider R4 and R10 and the impedance

network composed of R1, R2 and R3. When the one

shot has been triggered, the output of CMPTR2 is high,

causing the reference voltage at the non-inverting input

of CMPTR1 to go to VDD. This prevents any additional

input pulses from disturbing the circuit until the output

pulse has timed out.

The value of the timing capacitor C1 must be small

enough to allow CMPTR1 to discharge C1 to a diode

voltage before the feedback signal from CMPTR2

(through R10) switches CMPTR1 to its high state and

allows C1 to start an exponential charge through R5.

Proper circuit action depends upon rapidly discharging

C1 through the voltage set by R6, R9 and D2 to a final

voltage of a small diode drop. Two propagation delays

after the voltage on C1 drops below the level on the

non-inverting input of CMPTR2, the output of CMPTR1

switches to the positive rail and begins to charge C1

through R5. The time delay which sets the output pulse

width results from C1 charging to the reference voltage

set by R6, R9 and D2, plus four comparator propaga-

tion delays. When the voltage across C1 charges

beyond the reference, the output pulse returns to

ground and the input is again ready to accept a trigger

signal.

TC1025

4.4 Oscillators and Pulse Width

Modulators

Microchipâs linear building block comparators adapt

well to oscillator applications for low frequencies (less

than 100kHz). Figure 4-4 shows a symmetrical square

wave generator using a minimum number of compo-

nents. The output is set by the RC time constant of R4

and C1, and the total hysteresis of the loop is set by R1,

R2 and R3. The maximum frequency of the oscillator is

limited only by the large signal propagation delay of the

comparator in addition to any capacitive loading at the

output which degrades the slew rate. To analyze this

circuit, assume that the output is initially high. For this

to occur, the voltage at the inverting input must be less

than the voltage at the non-inverting input. Therefore,

capacitor C1 is discharged. The voltage at the

non-inverting input (VH) is:

EQUATION 4-5:

VH = [---R-----2---R--+---2--(-(-R--V---1-D----|D-|--R-)----3----)---]

where, if R1 = R2 = R3, then:

EQUATION 4-6:

2----(---V----D----D----)

Capacitor C1 will charge up through R4. When the

voltage at the comparatorâs inverting input is equal to

VH, the comparator output will switch. With the output

at ground potential, the value at the non-inverting input

terminal (VL) is reduced by the hysteresis network to a

value given by:

EQUATION 4-7:

-V----D---D--

Using the same resistors as before, capacitor C1 must

now discharge through R4 toward ground. The output

will return to a high state when the voltage across the

capacitor has discharged to a value equal to VL. The

period of oscillation will be twice the time it takes for the

RC circuit to charge up to one half its final value. The

period can be calculated from:

EQUATION 4-8:

--------1--------- = 2(0.694)(R4)(C1)

FREQ

DS21656C-page 5

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