RFRXD0420 Datasheet, PDF (5/32 Pages) Microchip Technology – UHF ASK/FSK/FM Receiver

2.0 CIRCUIT DESCRIPTION
This section gives a circuit description of the internal
circuitry of the rfRXD0420/0920 receiver. External
connections and components are given in the
APPLICATION CIRCUITS section.
2.1 Bias Circuitry
Bias circuitry provides bandgap biasing and circuit
shutdown capabilities. The ENRX (Pin 28) modes are
summarized in Table 2-1. The ENRX pin is a CMOS
compatible input and is internally pulled down to Vss.
TABLE 2-1: BIAS CIRCUITRY CONTROL
ENRX⁽¹⁾
Description
0
Standby mode
1
Receiver enabled
Note 1: ENRX has internal pull-down to Vss
2.2 Frequency Synthesizer
The Phase-locked Loop (PLL) frequency synthesizer
generates the Local Oscillator (LO) signal. It consists
of:
• Crystal oscillator
• Phase-frequency detector and charge pump
• Voltage Controlled Oscillator (VCO)
• Fixed feedback divider:
- rfRXD0420 = divide by 16
- rfRXD0920 = divide by 32
2.2.1 CRYSTAL OSCILLATOR
The internal crystal oscillator is a Colpitts type oscilla-
tor. It provides the reference frequency to the PLL. A
crystal is normally connected to the XTAL (Pin 26) and
ground. The internal capacitance of the crystal oscilla-
tor is 15 pF. Alternatively, a signal can be injected into
the XTAL pin from a signal source. The signal should
be AC coupled via a series capacitor at a level of
approximately 600 mV_pp.
The XTAL pin is illustrated in Figure 2-1.
FIGURE 2-1:
BLOCK DIAGRAM OF
XTAL PIN
VDD
XTAL
26
VSS
VDD
VDD
50 kΩ
30 pF
30 pF 40 µA
VSS
VSS
rfRXD0420/0920
The PLL consists of a phase-frequency detector,
charge pump, voltage-controlled oscillator (VCO), and
fixed divide-by-16 (rfRXD0420) or divide-by-32
(rfRXD0920) divider. The rfRXD0420/0920 employs a
charge pump PLL that offers many advantages over
the classical voltage phase detector PLL: infinite pull-in
range and zero steady state phase error. The charge
pump PLL allows the use of passive loop filters that are
lower cost and minimize noise. Charge pump PLLs
have reduced flicker noise thus limiting phase noise.
An external loop filter is connected to pin LF (Pin 29).
The loop filter controls the dynamic behavior of the
PLL, primarily lock time and spur levels. The applica-
tion determines the loop filter requirements.
The VCO gain for the rfRXD0420/0920 receivers are
listed in Table 2-2.
TABLE 2-2: PLL PARAMETERS
Device
rfRXD0420
KVCO(1)
250 MHz/V at
433 MHz
ICP(1)
60 µA
rfRXD0920 300 MHz/V at 60 µA
868 MHz
Note 1: Typical value
Divider
16
32
The LF pin is illustrated in Figure 2-2.
FIGURE 2-2: BLOCK DIAGRAM OF LOOP
FILTER PIN
VDD
LF
29
VSS
200 Ω
400 Ω
4 pF
VSS
VSS
2.3 Low Noise Amplifier
The Low-Noise Amplifier (LNA) is a high-gain amplifier
whose primary purpose is to lower the overall noise
figure of the entire receiver thus enhancing the receiver
sensitivity. The LNA is an open-collector cascode
design. The benefits of a cascode design are:
• high gain with low noise
• high-frequency
• wide bandwidth
• low effective input capacitance with stable input
impedance
• high output resistance
• high reverse isolation that provides improved
stability and reduces LO leakage
 2003 Microchip Technology Inc.
Preliminary
DS70090A-page 5