RFRXD0420 Datasheet, PDF (15/32 Pages) Microchip Technology – UHF ASK/FSK/FM Receiver

3.2 Amplitude Shift Keying (ASK)
Figure 3-9 illustrates an example ASK applications cir-
cuit.
The IF Limiting Amplifier with RSSI is used as an ASK
detector. The RSSI signal is post detector filtered and
then compared to a reference voltage to determine if
the incoming RF signal is a logical one or zero. The
reference voltage can be configured as a dynamic
voltage level determined by the incoming RF signal
strength or by a predetermined fixed level.
3.2.1 RSSI POST DETECTOR FILTERING
The RSSI signal is low-passed filtered to remove high
frequency and pulse noise to aid the decision making
process of the comparator and increase the sensitivity
of the receiver. The RSSI signal low-pass filter is a RC
filter created by the RSSI output impedance of 36 kΩ
and capacitor C1. Setting the time constant (RC = τ) of
the RC filter depends on the signal period and when the
signal decision will be made.
3.2.1.1 Signal Period
Optimum sensitivity of the receiver with reasonable
pulse distortion occurs when the RC filter time constant
is between 1 and 2 times the signal period. If the time
constant of the RC filter is set too short, there is little
noise filtering benefit. However, if the time constant of
the RC filter is set too long, the data pulses will become
elongated causing inter-symbol interference.
3.2.1.2 Signal Decision
If the bit decision occurs in the center of the signal
period (such as KEELOQ decoders), then one or two
times the RC filter time constant should be set at less
than or equal to half the signal period. Figure 3-10 illus-
trates this method. The top trace represents the
received on-off keying (OOK) signal. The bottom trace
shows the RSSI signal after the RC low-pass filter.
FIGURE 3-10: CENTER SIGNAL PERIOD
DECISION RSSI LOW-PASS
FILTERED
Signal Decision
OOK Signal
Signal Period
RSSI Signal
1τ to 2τ
rfRXD0420/0920
If the bit decision occurs near the end of the signal
period, then the time constant should be set at less
than or equal to the signal period. Figure 3-11
illustrates this method.
Once the signal decision time and time period of the
signal period are known, then capacitor C1 can be
selected. Once C1 is selected, the designer should
observe the RSSI signal with an oscilloscope and
perform operational and/or bit error rate testing to
confirm receiver performance.
FIGURE 3-11: NEAR END OF THE SIGNAL
PERIOD DECISION RSSI LOW-
PASS FILTERED
Signal Decision
OOK Signal
Signal Period
RSSI Signal
1τ to 2τ
3.2.2 COMPARATOR
The internal operational amplifier is configured as a
comparator. The RSSI signal is applied to OPA+ (Pin
20) and compared with a reference voltage on OPA-
(Pin 19) to determine the logic level of the received
signal. The reference voltage can be dynamic or static.
The choice of dynamic versus static reference voltage
depends in part on the ratio of logical ones versus
zeros of the data (this can also be thought of as the AC
content of the data). Provided the ratio has an even
number of logical ones versus zeros, a dynamic refer-
ence voltage can be generated with a simple low-pass
filter. The advantage of the dynamic reference voltage
is the increased receiver sensitivity compared to a fixed
reference voltage. However, the comparator will output
random data. The decoder (for example, a pro-
grammed PICmicro MCU or KEELOQ decoder) must
distinguish between random noise and valid data.
The choice of a static reference voltage depends in part
on the DC content of the data. That is, the data has an
uneven number of logical ones versus zeros. The
disadvantage of the static reference voltage is
decreased receiver sensitivity compared to a dynamic
reference voltage. In this case, the comparator will
output data without random noise.
 2003 Microchip Technology Inc.
Preliminary
DS70090A-page 15