93LC56AB Datasheet, PDF (5/12 Pages) Microchip Technology – 2K 2.5V Microwave Serial EEPROM

3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2: ERASE TIMING
CS
CLK
93LC56A/B
3.5 Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences at
the falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
TCSL
CHECK STATUS
DI
1
1
1
AN AN-1 AN-2 •••
A0
HIGH-Z
DO
FIGURE 3-3: ERAL TIMING
TCSL
CS
TSV
BUSY
TWC
TCZ
READY
HIGH-Z
CHECK STATUS
CLK
DI
1
0
0
10
X •••
X
HIGH-Z
DO
Guaranteed at Vcc = 4.5V to +6.0V.
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
© 1997 Microchip Technology Inc.
Preliminary
DS21208A-page 5