24C01B Datasheet, PDF (5/13 Pages) Microchip Technology – 1K/2K 5.0V I 2 C ™ Serial EEPROM

24C01B/02B
3.6 Device Address
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01B/02B
(Figure 3-2).
The 24C01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
Operation
Control
Code
Chip
Select
R/W
Read
1010
XXX
1
Write
1010
XXX
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
X
X
X
X = Don’t care
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
CONTROL
A
BYTE
R
T
SDA LINE
S
A
BUS ACTIVITY
C
K
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24C01B/02B. After
receiving another acknowledge signal from the
24C01B/02B the master device will transmit the data
word to be written into the addressed memory location.
The 24C01B/02B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24C01B/02B will
not generate acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24C01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
WORD
ADDRESS
A
C
K
DATA
S
T
O
P
P
A
C
K
FIGURE 4-2: PAGE WRITE
BUS ACTIVITY ^S
MASTER
T
A
R
T
SDA LINE
S
CONTROL
BYTE
BUS ACTIVITY
WORD
ADDRESS (n)
A
A
C
C
K
K
DATA n
DATAn + 1
S
DATAn + 7
T
O
P
P
A
A
A
C
C
C
K
K
K
© 1997 Microchip Technology Inc.
Preliminary
DS21233A-page 5