24AA014_10 Datasheet, PDF (5/36 Pages) Microchip Technology – 1K I2C™ Serial EEPROM

24AA014/24LC014
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name PDIP
SOIC TSSOP DFN⁽¹⁾ TDFN⁽¹⁾ MSOP SOT-23
Description
A0
1
1
1
1
1
1
5 Chip Address Input
A1
2
2
2
2
2
2
4 Chip Address Input
A2
3
3
3
3
3
3
— Chip Address Input
VSS
4
4
4
4
4
4
2 Ground
SDA
5
5
5
5
5
5
3 Serial Address/Data I/O
SCL
6
6
6
6
6
6
1 Serial Clock
WP
7
7
7
7
7
7
— Write-Protect Input
VCC
8
8
8
8
8
8
6 +1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24AA014/
24LC014 for multiple device operation. The levels on
these inputs are compared with the corresponding bits
in the slave address. The chip is selected if the com-
pare is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
For the SOT-23 devices up to four devices may be con-
nected to the same bus using different Chip Select bit
combinations.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24AA014/24LC014 supports a bidirectional, 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, while
a device receiving data is defined as a receiver. The
bus has to be controlled by a master device which gen-
erates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while the
24AA014/24LC014 works as slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is activated.
 2010 Microchip Technology Inc.
DS21809G-page 5