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TC3403_05 Datasheet, PDF (4/16 Pages) Microchip Technology – +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor and Microprocessor Reset Circuit | |||
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TC3403
TC3403 DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TA = 25°C and VDD = 2.7V, unless otherwise specified. Boldface type specifications apply for
temperatures of 0°C to 85°C. VREF = 1.25V, Internal Clock Frequency = 520kHz.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
SCLK, A0, A1, ENABLE
VIL
VIH
ILEAK
Input Low Voltage
Input High Voltage
Leakage Current
SDAT, RESET, PFO
â
0.7 x VDD
â
VOL
VOH
VDDMIN
Output Low Voltage
Output High Voltage (SDAT)
Minimum VDD for PFO, RESET Valid
â
0.9 x VDD
â
VTH, PFI
VCCPFI
PFI Input Voltage Range
0
VTH, PFI Input Current
-0.1
VTHR
Threshold (VTH, PFI)
â
Threshold Hysteresis
â
Threshold Tempco
â
Note 1: Differential input voltage defined as (VIN+ â VIN-).
2: Resistance from INn+ to INn- or INn to GND.
3: @ VDD = 1.8V, ISOURCE ⤠200μA.
â
â
1
â
â
1.1
â
.01
1.23
30
30
0.3 x VDD
V
â
V
â
μA
0.4
V IOL = 1.5mA
â
V ISOURCE = 400μA (Note 3)
1.3
μA
VDD
V
0.1
μA
â
V
â
mV
â
ppm/°C
TC3403 AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TA = 25°C and VDD = 2.7V, unless otherwise specified. Boldface type specifications apply for
temperatures of 0°C to 85°C. VREF = 1.25V, Internal Clock Frequency = 520kHz.
Symbol
Parameter
Min
Typ
Max Unit
Test Conditions
t1
Resolution Reduction Clock Width
1
â
â
µsec Width of SCLK (Negative)
t2
Resolution Reduction Clock Width
1
â
â
µsec Width of SCLK (Positive)
t3
Conversion Time (15-bit Plus Sign) â
125
â
msec 16-bit Conversion, TA = 25°C (Note 1)
Conversion Time (14-bit Plus Sign) â
t3/2.0
â
msec 15-bit Conversion
Conversion Time (13-bit Plus Sign) â
t3/4.0
â
msec 14-bit Conversion
Conversion Time (12-bit Plus Sign) â
t3/7.8
â
msec 13-bit Conversion
Conversion Time (11-bit Plus Sign) â
t3/15.1
â
msec 12-bit Conversion
Conversion Time (10-bit Plus Sign) â
t3/28.6
â
msec 11-bit Conversion
Conversion Time (9-bit Plus Sign)
â
t3/51.4
â
msec 10-bit Conversion
t4
Resolution Reduction Window
â
t3/85.7
â
msec Width of SCLK
t5
SCLK to Data Valid
1000
â
â
nsec SCLK Falling Edge to SDAT Valid
t6
Address Setup
0
â
â
nsec Address Valid to SCLK
t7
Address Hold
1000
â
â
nsec SCLK to Address Valid Hold
t8
Acknowledge Delay
â
â
1000 nsec SCLK to SDAT Delay
t9
RESET Active Timeout Period
â
t3*2
â
msec Delay from POR or Brown-out
Recovery to RESET = VOH
t10
PFO Delay
â
25
â
µsec PFI to PFO Delay
t11
RESET Delay
5
â
64
µsec Delay VTH Falling at 10V/msec to
RESET Low
Note 1: Nominal temperature drift is -2830ppm/C° for temperature less than 25°C and -1340ppm/°C for temperatures
greater than 25°C.
DS21412C-page 4
© 2005 Microchip Technology Inc.
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