TC3403_05 Datasheet, PDF(10/16 Page) Microchip Technology – +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor and Microprocessor Reset Circuit

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TC3403_05 Datasheet, PDF (10/16 Pages) Microchip Technology – +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor and Microprocessor Reset Circuit

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TC3403

3.3 VDD Monitor

The TC3403 RESET output is high impedance pro-

vided the voltage at VTH is greater than the internal

voltage reference. This reference is approximately the

same value as the voltage appearing at REFOUT. When

VTH is less than the internal reference, RESET is pulled

low. When VTH rises above the internal reference

voltage again, RESET is held low for the reset active

timeout period, t9, before being released. The RESET

output is ensured to be valid for VDD = 1.3V to 5.5V.

When used to generate a Power-on or Brown-out

Reset, an external resistor network is required to divide

the appropriate VDD threshold down to 1.23V at the

VTH input, (See the Typical Application circuit). For

example, to generate a POR for a VDD at 3V- 10%, then

the values of R1 and R2 should be 137kÎ© and 115kÎ©

respectively.

Since RESET is an open drain, it can be wired-ORâed

with another open drain or external switch if desired.

3.4 Power Fail Detector

The Power Fail detector is a comparator in which the

inverting input is connected to the internal voltage

reference. The non-inverting input is the PFI pin of the

TC3403 and the PFO pin is the active low, open drain

output. This comparator is suitable as an early warning

fail or low battery indicator. In a typical application,

where a voltage regulator is being used to supply

power to a system, the Power Fail comparator would

monitor the input voltage to the regulator while the VDD

monitor would measure the output voltage of the

regulator. Both PFO and RESET would drive interrupt

pins of a microcontroller.

The Power Fail detector may be used as a Wake-up or

Watchdog Timer. The Typical Application circuit shows

an RC network on PFI with the capacitor tied to a

time constant is roughly ten seconds. The Î¼C resets

the RC network by driving the I/O tied to PFI low and

then tristating it. The RC network will ramp to 1.23V in

roughly 9 seconds, assuming a VBATT of 3.0V. With

PFO tied to a Î¼C input or interrupt, the Î¼C will see a low

to high transition on PFO when the voltage on PFI

exceeds 1.23V. The PFO output is specified to be valid

for VDD = 1.3 to 5.5V.

DS21412C-page 10

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