PIC18F46J50 Datasheet, PDF (4/12 Pages) Microchip Technology – PIC18F46J50 Family Silicon Errata and Data Sheet Clarification

PIC18F46J50 FAMILY
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTAx<7> = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
after setting SPEN = 1
Work around
Add a 2 TCY delay after any instruction that re-
enables the EUSART module (sets SPEN = 1).
Refer to Example 1.
EXAMPLE 1: RE-ENABLING A EUSART MODULE
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop ;1 Tcy delay
nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
Affected Silicon Revisions
A2 A4
XX
DS80436C-page 4
 2010 Microchip Technology Inc.