PIC18F46J50 Datasheet, PDF (2/12 Pages) Microchip Technology – PIC18F46J50 Family Silicon Errata and Data Sheet Clarification

PIC18F46J50 FAMILY
TABLE 2: SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
MSSP
MSSP
I²C™
Modes
I²C Slave
1.
Must keep LATB<5:4> bits clear.
2.
Module may not receive the correct data if there
is a delay in reading SSPxBUF after SSPxIF
interrupt.
EUSART
Enable/Dis-
able
3.
If interrupts are enabled, a 2 TCY delay needed
after re-enabling the module.
A/D
FOSC/2
4.
FOSC/2 A/D Conversion mode may not meet
Clock
linearity error limits.
PMP
PSP
5.
Incorrect data capture in Slave modes.
Low-Power
modes
Deep Sleep
6.
Wake-up events that occur during Deep Sleep
entry may not generate an event.
DC
Characteristics
Supply Volt-
age
7.
Minimum operating voltage (VDD) parameter for
“F” devices is 2.25V.
A/D
Band Gap
8.
At high VDD voltages, performing an A/D
Reference
conversion on Channel 15 could have issues.
CTMU
Constant
Current
9.
Low voltages turn off constant current source.
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
Affected
Revisions⁽¹⁾
A2
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80436C-page 2
 2010 Microchip Technology Inc.