24C65 Datasheet, PDF (4/24 Pages) Microchip Technology – 64K 5.0V I 2 C Smart Serial EEPROM

24AA65/24LC65/24C65
TABLE 1-2: AC CHARACTERISTICS
Parameter
VCC = 1.8V-6.0V
Symbol ^{STD. Mode}
Min Max
VCC = 4.5-6.0V
FAST Mode
Min Max
Units
Remarks
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
THIGH
4000
—
600
—
ns
Clock low time
TLOW
4700
—
1300
—
ns
SDA and SCL rise time
TR
— 1000
—
300
ns (Note 1)
SDA and SCL fall time
TF
—
300
—
300
ns (Note 1)
Start condition setup time
THD:STA 4000
—
600
—
ns After this period the first
clock pulse is generated
Start condition setup time
TSU:STA 4700
—
600
—
ns Only relevant for
repeated Start condition
Data input hold time
THD:DAT 0
—
0
—
ns
Data input setup time
TSU:DAT 250
—
100
—
ns
Stop condition setup time
TSU:STO 4000
—
600
—
ns
Output valid from clock
TAA
— 3500
—
900
ns (Note 2)
Bus free time
TBUF
4700 —
1300
—
ns Time the bus must be
free before a new
transmission can start
Output fall time from VIH min to TOF
VIL max
—
250 20 + 0.1 250
ns (Note 1), CB ≤ 100 pF
CB
Input filter spike suppression TSP
(SDA and SCL pins)
50
—
50
—
ns (Note 3)
Write cycle time
TWR
—
5
—
5 ms/page (Note 4)
Endurance
High Endurance Block
Rest of Array
10M —
1M
—
10M
1M
— cycles 25°C, (Note 5)
—
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.
FIGURE 1-2:
BUS TIMING DATA
TF
SCL
TSU:STA
SDA
IN
SDA
OUT
TSP
TAA
TLOW
THD:STA
THIGH
THD:DAT
TAA
TR
TSU:DAT _TSU:STO
TBUF
DS21073K-page 4
© 2008 Microchip Technology Inc.