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PIC18F4680-I Datasheet, PDF (399/482 Pages) Microchip Technology – PIC18F2585/2680/4585/4680 Data Sheet | |||
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PIC18F2585/2680/4585/4680
SUBLW
Subtract W from Literal
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
SUBLW k
0 ⤠k ⤠255
k â (W) â W
N, OV, C, DC, Z
0000 1000 kkkk kkkk
W is subtracted from the eight-bit
literal âkâ. The result is placed in W.
1
1
Q2
Read
literal âkâ
Q3
Process
Data
Q4
Write to W
Example 1:
SUBLW 02h
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
01h
?
01h
1 ; result is positive
0
0
Example 2:
SUBLW 02h
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
02h
?
00h
1 ; result is zero
1
0
Example 3:
SUBLW 02h
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
03h
?
FFh; (2âs complement)
0 ; result is negative
0
1
SUBWF
Subtract W from f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
SUBWF f {,d {,a}}
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f) â (W) â dest
N, OV, C, DC, Z
0101 11da ffff ffff
Subtract W from register âfâ (2âs
complement method). If âdâ is â0â, the
result is stored in W. If âdâ is â1â, the
result is stored back in register âfâ
(default).
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ⤠95 (5Fh). See
Section 25.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWF REG, 1, 0
Before Instruction
REG = 3
W
=2
C
=?
After Instruction
REG = 1
W
=2
C
=1
Z
=0
N
=0
; result is positive
Example 2:
SUBWF REG, 0, 0
Before Instruction
REG
W
=2
=2
C
=?
After Instruction
REG
W
=2
=0
C
=1
Z
=1
N
=0
; result is zero
Example 3:
SUBWF REG, 1, 0
Before Instruction
REG =
W
=
C
=
After Instruction
REG =
W
=
C
=
Z
=
N
=
1
2
?
FFh ;(2âs complement)
2
0 ; result is negative
0
1
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 397
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