PIC16F1826-I Datasheet, PDF (394/400 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16F/LF1826/27
Accessing.................................................................... 40
Reset........................................................................... 42
Stack Overflow/Underflow................................................... 76
STATUS Register................................................................ 21
SUBWFB........................................................................... 333
T
T1CON Register.......................................................... 28, 183
T1GCON Register............................................................. 184
T2CON Register............................................................ 28, 36
Thermal Considerations .................................................... 349
Timer0 ............................................................................... 171
Associated Registers ................................................ 173
Operation .................................................................. 171
Specifications ............................................................ 357
Timer1
Associated registers.................................................. 185
Asynchronous Counter Mode ................................... 177
Reading and Writing ......................................... 177
Clock Source Selection ............................................. 176
Interrupt..................................................................... 179
Operation .................................................................. 176
Operation During Sleep ............................................ 179
Oscillator ................................................................... 177
Prescaler ................................................................... 177
Specifications ............................................................ 357
Timer1 Gate
Selecting Source............................................... 177
TMR1H Register ....................................................... 175
TMR1L Register ........................................................ 175
Timer2
Associated registers.................................................. 190
Timer2/4/6 ......................................................................... 187
Associated registers.................................................. 190
Timers
Timer1
T1CON.............................................................. 183
T1GCON ........................................................... 184
Timer2/4/6
TxCON .............................................................. 189
Timing Diagrams
A/D Conversion ......................................................... 359
A/D Conversion (Sleep Mode) .................................. 359
Acknowledge Sequence ........................................... 270
Asynchronous Reception .......................................... 292
Asynchronous Transmission ..................................... 288
Asynchronous Transmission (Back to Back) ............ 288
Auto Wake-up Bit (WUE) During Normal Operation . 304
Auto Wake-up Bit (WUE) During Sleep .................... 304
Automatic Baud Rate Calibration .............................. 302
Baud Rate Generator with Clock Arbitration ............. 263
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 274
Brown-out Reset (BOR) ............................................ 355
Brown-out Reset Situations ........................................ 75
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 275
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 275
Bus Collision During a Start Condition (SCL = 0) ..... 274
Bus Collision During a Stop Condition (Case 1) ....... 276
Bus Collision During a Stop Condition (Case 2) ....... 276
Bus Collision During Start Condition (SDA only) ...... 273
Bus Collision for Transmit and Acknowledge............ 272
CLKOUT and I/O....................................................... 353
Clock Synchronization .............................................. 260
Clock Timing ............................................................. 351
Comparator Output ................................................... 155
Enhanced Capture/Compare/PWM (ECCP)............. 357
Fail-Safe Clock Monitor (FSCM)................................. 64
First Start Bit Timing ................................................. 264
Full-Bridge PWM Output........................................... 218
Half-Bridge PWM Output .................................. 216, 224
I²C Bus Data............................................................. 365
I²C Bus Start/Stop Bits ............................................. 364
I²C Master Mode (7 or 10-Bit Transmission) ............ 267
I²C Master Mode (7-Bit Reception)........................... 269
I²C Stop Condition Receive or Transmit Mode......... 271
INT Pin Interrupt ......................................................... 85
Internal Oscillator Switch Timing ................................ 59
PWM Auto-shutdown ................................................ 223
Firmware Restart .............................................. 223
PWM Direction Change ............................................ 219
PWM Direction Change at Near 100% Duty Cycle... 220
PWM Output (Active-High) ....................................... 214
PWM Output (Active-Low) ........................................ 215
Repeat Start Condition ............................................. 265
Reset Start-up Sequence ........................................... 77
Reset, WDT, OST and Power-up Timer ................... 354
Send Break Character Sequence ............................. 305
SPI Master Mode (CKE = 1, SMP = 1) ..................... 362
SPI Mode (Master Mode).......................................... 237
SPI Slave Mode (CKE = 0) ....................................... 363
SPI Slave Mode (CKE = 1) ....................................... 363
Synchronous Reception (Master Mode, SREN) ....... 309
Synchronous Transmission ...................................... 307
Synchronous Transmission (Through TXEN) ........... 307
Timer0 and Timer1 External Clock ........................... 356
Timer1 Incrementing Edge ....................................... 179
Two Speed Start-up.................................................... 62
USART Synchronous Receive (Master/Slave) ......... 361
USART Synchronous Transmission (Master/Slave). 361
Wake-up from Interrupt............................................... 98
Timing Diagrams and Specifications
PLL Clock ................................................................. 352
Timing Parameter Symbology .......................................... 350
Timing Requirements
I²C Bus Data............................................................. 366
SPI Mode .................................................................. 364
TMR0 Register.................................................................... 28
TMR1H Register ................................................................. 28
TMR1L Register.................................................................. 28
TMR2 Register.............................................................. 28, 36
TRIS.................................................................................. 334
TRISA Register........................................................... 29, 118
TRISB ............................................................................... 123
TRISB Register........................................................... 29, 124
Two-Speed Clock Start-up Mode........................................ 61
TXCON (Timer2/4/6) Register .......................................... 189
TxCON Register ............................................................... 229
TXREG ............................................................................. 287
TXREG Register ................................................................. 31
TXSTA Register.......................................................... 31, 294
BRGH Bit .................................................................. 297
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 361
Requirements, Synchronous Transmission...... 361
Timing Diagram, Synchronous Receive ........... 361
Timing Diagram, Synchronous Transmission... 361
DS41391B-page 394
Preliminary
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