SST26VF064B_15 Datasheet, PDF (38/85 Pages) Microchip Technology – 2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory

SST26VF064B / SST26VF064BA
5.36 Non-Volatile Write-Lock Lock-
Down Register (nVWLDR)
The Non-Volatile Write-Lock Lock-Down Register
(nVWLDR) instruction controls the ability to change the
Write-Lock bits in the Block-Protection register. Exe-
cute WREN before initiating the nVWLDR instruction.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.
After CE# goes high, the non-volatile bits are pro-
grammed and the programming time-out must com-
plete before any additional commands, other than
Read Status Register, can be entered. Poll the BUSY
bit in the Status register, or wait T_PP, for the completion
of the internal, self-timed, Write operation. Data inputs
must be most significant bit(s) first.
FIGURE 5-42:
WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
CE#
MODE 3 0
2
4
6
8
10
12
SCK _{MODE 0}
SIO(3:0)
E 8 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
MSN LSN
BPR [m:m-7]
Note:
MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write-Lock Lock-Down Register (nVWLDR) m = 143
HN LN
BPR [7:0]
25119 F36.0
FIGURE 5-43:
WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)
CE#
MODE 3
SCK MODE 0
SI
0 1 2345 6 78
15 16
23 24 31 32
OP Code
E8H
Data Byte0 Data Byte1 Data Byte2
SO
Data ByteN
25119 F69.1
DS20005119G-page 38
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