MCP79400_16 Datasheet, PDF (37/62 Pages) Microchip Technology – Battery-Backed I2C Real-Time Clock/Calendar with SRAM and Protected EEPROM

MCP79400/MCP79401/MCP79402
6.2 Protected EEPROM
The MCP7940X features a 64-bit protected EEPROM
block that requires a special unlock sequence to be
followed in order to write to the memory. Note that
reading from the memory does not require the unlock
sequence to be performed. The protected EEPROM
can be used for storing crucial information such as a
unique serial number. The MCP79401 and MCP79402
include an EUI-48 and EUI-64 node address,
respectively, pre-programmed into the protected
EEPROM block. Custom programming is also
available.
The protected EEPROM block is located at addresses
0xF0 to 0xF7 and is accessed using the ‘1010111X’
control byte.
Note:
Attempts to access addresses outside of
0xF0 to 0xF7 will result in the MCP7940X
not acknowledging the address.
6.2.1
PROTECTED EEPROM UNLOCK
SEQUENCE
The protected EEPROM block requires a special
unlock sequence to prevent unintended writes, utilizing
the EEUNLOCK register. The EEUNLOCK register is
not a physical register; it is used exclusively in the
EEPROM write sequence. Reading from EEUNLOCK
will read all 0’s.
To unlock the block, the following sequence must be
followed:
1. Write 0x55 to the EEUNLOCK register
2. Write 0xAA to the EEUNLOCK register
3. Write the desired data bytes to the EEPROM
Figure 6-6 illustrates the sequence.
Note 1: Diverging from any step of the unlock
sequence may result in the EEPROM
remaining locked and the write operation
being ignored.
2: Unlocking the EEPROM is not required in
order to read from the memory.
The entire EEPROM block does not have to be written
in a single operation. However, the block is locked after
each write operation and must be unlocked again to
start a new Write command.
6.2.2
PROTECTED EEPROM BYTE
WRITE
Following the unlock sequence and the Start condition
from the master, the control code and the R/W bit
(which is a logic low) are clocked onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that the address byte will follow after it
has generated an Acknowledge bit during the ninth
clock cycle.
Therefore, the next byte transmitted by the master is
the address and will be written into the Address Pointer
of the MCP7940X. After receiving another
Acknowledge bit from the MCP7940X, the master
device transmits the data byte to be written into the
addressed memory location. The MCP7940X
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and,
during this time, the MCP7940X does not generate
Acknowledge signals for protected EEPROM
commands. Access to the RTCC registers and SRAM
is still possible during an EEPROM write cycle.
If an attempt is made to write to an address outside of
the 0xF0 to 0xF7 range, the MCP7940X will not
acknowledge the address or data bytes, no data will be
written, and the device will immediately accept a new
command. After a byte write command, the internal
Address Pointer will point to the address location
following the one that was just written.
6.2.3
PROTECTED EEPROM
SEQUENTIAL WRITE
The unlock sequence, write control byte, word address,
and the first data byte are transmitted to the
MCP7940X in the same way as in a byte write. But
instead of generating a Stop condition, the master
transmits up to seven additional bytes, which are
temporarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
Stop condition. After receipt of each word, the three
lower Address Pointer bits are internally incremented
by one. If the master should transmit more than eight
bytes prior to generating the Stop condition, the
address counter will roll over and the data received
previously will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-6).
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DS20005009F-page 37