USB3250 Datasheet, PDF (35/46 Pages) Microchip Technology – Hi-Speed USB Device Transceiver with UTMI Interface

USB3250
Note 8-5
Due to the assertion of the HS termination on the host port and FS termination on the device port,
between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are less
than FS signaling levels.
8.10 HS Detection Handshake - Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are assumed to be pow-
ered down. Figure 8-6 shows how CLK60 is used to control the duration of the chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE), SUSPENDN is combina-
torially negated at time T0 by the SIE. It takes approximately 5 milliseconds for the transceiver's oscillator to stabilize.
The device does not generate any transitions of the CLK60 signal until it is "usable" (where "usable" is defined as stable
to within ±10% of the nominal frequency and the duty cycle accuracy 50±5%).
The first transition of CLK60 occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding,
XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLK60 cycles to ensure a 1ms minimum duration. If
CLK60 is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLK60 is 10% slow (54 MHz) then Chirp K will be 1.2ms. The
5.6ms requirement for the first CLK60 transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and
still complete before T3. Once the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLK60
to time the process. At this time, the device follows the same protocol as in section 8.9 for completion of the High Speed
Handshake.
FIGURE 8-6:
HS DETECTION HANDSHAKE TIMING BEHAVIOR FROM SUSPEND
T0
time
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
SUSPENDN
TXVALID
CLK60
DP/DM
J
T1 T2
T3 T4
SE0
CLK power up time
Device Chirp K Look for host chirps
To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the SIE must see the appropriate
LINESTATE signals asserted continuously for 165 CLK60 cycles.
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DS00002142A-page 35