DSPIC30F3012-30IP Datasheet, PDF (32/210 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC30F2011/2012/3012/3013
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL
instructions offer a direct method of reading or writing
the lsw of any address within program space, without
going through data space. The TBLRDH and TBLWTH
instructions are the only method whereby the upper 8
bits of a program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the lsw, and TBLRDH
and TBLWTH access the space which contains the
MSB.
Figure 3-2 shows how the EA is created for table
operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of table instructions are provided to move byte or
word-sized data to and from program space. See
Figure 3-4 and Figure 3-5.
1. TBLRDL: Table Read Low
Word: Read the LS Word of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSB of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
2. TBLWTL: Table Write Low (refer to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
3. TBLRDH: Table Read High
Word: Read the MS Word of the program address;
P<23:16> maps to D<7:0>; D<15:8> will always
be = 0.
Byte: Read one of the MSB of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4. TBLWTH: Table Write High (refer to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (lsw)
PC Address
23
16
8
0
0x000000
00000000
0x000002
00000000
0x000004
00000000
0x000006
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
TBLRDL.W
TBLRDL.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
DS70139G-page 32
© 2010 Microchip Technology Inc.