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DSPIC30F3012-30IP Datasheet, PDF (132/210 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers
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dsPIC30F2011/2012/3012/3013
Table 17-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.
TABLE 17-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000 0
0
0
0
0
0
0
11
Brown-out Reset
0x000000
0
0
0
0
0
0
0
01
MCLR Reset during normal 0x000000 0
operation
0
1
0
0
0
0
00
Software Reset during
normal operation
0x000000 0
0
0
1
0
0
0
00
MCLR Reset during Sleep 0x000000 0
0
1
0
0
0
1
00
MCLR Reset during Idle
0x000000 0
0
1
0
0
1
0
00
WDT Time-out Reset
0x000000 0
0
0
0
1
0
0
00
WDT Wake-up
Interrupt Wake-up from
Sleep
PC + 2
0
PC + 2(1)
0
0
0
0
1
0
1
00
0
0
0
0
0
1
00
Clock Failure Trap
0x000004 0
0
0
0
0
0
0
00
Trap Reset
0x000000 1
0
0
0
0
0
0
00
Illegal Operation Trap
0x000000 0
1
0
0
0
0
0
00
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 17-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 17-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000 0
0
0
0
0
0
0
11
Brown-out Reset
0x000000 u
u
u
u
u
u
u
01
MCLR Reset during normal 0x000000 u
operation
u
1
0
0
0
0
uu
Software Reset during
normal operation
0x000000 u
u
0
1
0
0
0
uu
MCLR Reset during Sleep 0x000000 u
u
1
u
0
0
1
uu
MCLR Reset during Idle
0x000000 u
u
1
u
0
1
0
uu
WDT Time-out Reset
0x000000 u
u
0
0
1
0
0
uu
WDT Wake-up
Interrupt Wake-up from
Sleep
PC + 2
u
PC + 2(1)
u
u
u
u
1
u
1
uu
u
u
u
u
u
1
uu
Clock Failure Trap
0x000004 u
u
u
u
u
u
u
uu
Trap Reset
0x000000 1
u
u
u
u
u
u
uu
Illegal Operation Reset
0x000000 u
1
u
u
u
u
u
uu
Legend: u = unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70139G-page 132
© 2010 Microchip Technology Inc.
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