PIC18F2458 Datasheet, PDF(30/46 Page) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology

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PIC18F2458 Datasheet, PDF (30/46 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology

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PIC18F2458/2553/4458/4553

2.8 Use of the CCP2 Trigger

An A/D conversion can be started by the Special Event

Trigger of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as â1011â and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the GO/

DONE bit will be set, starting the A/D acquisition and

conversion, and the Timer1 (or Timer3) counter will be

reset to zero. Timer1 (or Timer3) is reset to automatically

repeat the A/D acquisition period with minimal software

overhead (firmware must move ADRESH:ADRESL to

the desired location). The appropriate analog input

channel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate TACQ

time selected before the Special Event Trigger sets the

GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

INTCON

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

ADRESH

ADRESL

GIE/GIEH PEIE/GIEL

SPPIF(1)

ADIF

SPPIE(1) ADIE

SPPIP(1) ADIP

TMR0IE

RCIF

RCIE

RCIP

OSCFIF CMIF USBIF

OSCFIE CMIE USBIE

OSCFIP CMIP USBIP

A/D Result Register High Byte

A/D Result Register Low Byte

INT0IE

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

Bit 3

RBIE

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

Bit 2

TMR0IF

CCP1IF

CCP1IE

CCP1IP

HLVDIF

HLVDIE

HLVDIP

Bit 1

INT0IF

TMR2IF

TMR2IE

TMR2IP

TMR3IF

TMR3IE

TMR3IP

Bit 0

Reset

Values

on Page:

RBIF

(4)

TMR1IF

(4)

TMR1IE

(4)

TMR1IP

(4)

CCP2IF

(4)

CCP2IE

(4)

CCP2IP

(4)

ADCON0

CHS3

CHS2

CHS1 CHS0 GO/DONE ADON

ADCON1

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

ADCON2 ADFM

ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

PORTA

RA6(2)

RA5

RA4

RA3

RA2

RA1

RA0

(4)

TRISA

TRISA6(2) PORTA Data Direction Control Register

(4)

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

(4)

TRISB PORTB Data Direction Control Register

(4)

LATB

PORTB Data Latch Register (Read and Write to Data Latch)

(4)

PORTE(1) RDPU

RE3(3)

RE2(1)

RE1(1)

RE0(1)

(4)

TRISE(1)

TRISE2 TRISE1 TRISE0

(4)

LATE(1)

â PORTE Data Latch Register

(4)

Legend:

Note 1:

â = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

These registers and/or bits are not implemented on 28-pin devices and are read as â0â.

RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;

otherwise, they are read as â0â.

RE3 port bit is available only as an input pin when the MCLRE Configuration bit is â0â.

For these Reset values, see the âPIC18F2455/2550/4455/4550 Data Sheetâ.

DS39887B-page 28

Preliminary

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