PIC18F2458 Datasheet, PDF (17/46 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology

PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
PDIP QFN TQFP ^{Type Type}
Description
PORTB is a bidirectional I/O port. PORTB can be soft-
ware programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33 9
8
I/O TTL
I Analog
I ST
I ST
I ST
I/O ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I²C™ data I/O.
RB1/AN10/INT1/SCK/ 34 10 9
SCL
RB1
I/O TTL Digital I/O.
AN10
I Analog Analog input 10.
INT1
I
ST
External interrupt 1.
SCK
SCL
I/O ST
I/O ST
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I²C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35 11 10
I/O TTL Digital I/O.
I Analog Analog input 8.
I
ST
External interrupt 2.
O—
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2⁽¹⁾
VPO
36 12
11
I/O TTL Digital I/O.
I Analog Analog input 9.
I/O ST
Capture 2 input/Compare 2 output/PWM 2 output.
O—
External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP 37 14 14
RB4
I/O TTL Digital I/O.
AN11
I Analog Analog input 11.
KBI0
I TTL Interrupt-on-change pin.
CSSPP
O—
SPP chip select control output.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15
15
I/O TTL
I TTL
I/O ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16
16
I/O TTL
I TTL
I/O ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17
17
I/O TTL
I TTL
I/O ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I
= Input
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39887B-page 15