PIC16F84A_13 Datasheet, PDF (30/90 Pages) Microchip Technology – 18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller

PIC16F84A
6.9 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
The code in Example 6-1 stores and restores the
STATUS and W register’s values. The user defined
registers, W_TEMP and STATUS_TEMP are the tem-
porary storage locations for the W and STATUS
registers values.
Example 6-1 does the following:
a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit)
register.
e) Restores the W register.
EXAMPLE 6-1:
PUSH MOVWF
SWAPF
MOVWF
ISR
:
:
:
:
POP
SWAPF
MOVWF
SWAPF
SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP
; Copy W to TEMP register,
STATUS, W
; Swap status to be saved into W
STATUS_TEMP
; Save status to STATUS_TEMP register
:
; Interrupt Service Routine
; should configure Bank as required
;
STATUS_TEMP,W
; Swap nibbles in STATUS_TEMP register
; and place result into W
STATUS
; Move W into STATUS register
; (sets bank to original state)
W_TEMP, F
; Swap nibbles in W_TEMP and place result in W_TEMP
W_TEMP, W
; Swap nibbles in W_TEMP and place result into W
6.10 Watchdog Timer (WDT)
The Watchdog Timer is a free running On-Chip RC
Oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 6.1).
6.10.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
DS35007C-page 30
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