24AA512_05 Datasheet, PDF (3/26 Pages) Microchip Technology – 512K I2C™ CMOS Serial EEPROM

24AA512/24LC512/24FC512
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
FCLK Clock frequency
2
THIGH Clock high time
—
—
—
4000
600
500
100
400
1000
—
—
—
kHz 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
3
TLOW Clock low time
4700
—
ns 1.8V ≤ VCC < 2.5V
1300
—
2.5V ≤ VCC ≤ 5.5V
500
—
2.5V ≤ VCC ≤ 5.5V 24FC512
4
TR
SDA and SCL rise time (Note 1)
—
—
—
1000
300
300
ns 1.8V ≤ VCC< 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
5
TF
SDA and SCL fall time (Note 1)
—
—
300
ns All except, 24FC512
100
2.5V ≤ VCC ≤ 5.5V 24FC512
6
THD:STA Start condition hold time
4000
—
ns 1.8V ≤ VCC < 2.5V
600
—
2.5V ≤ VCC ≤ 5.5V
250
—
2.5V ≤ VCC ≤ 5.5V 24FC512
7
TSU:STA Start condition setup time
4700
—
ns 1.8V ≤ VCC < 2.5V
600
—
2.5V ≤ VCC ≤ 5.5V
250
—
2.5V ≤ VCC ≤ 5.5V 24FC512
8
THD:DAT Data input hold time
0
—
ns (Note 2)
9
TSU:DAT Data input setup time
250
—
ns 1.8V ≤ VCC < 2.5V
100
—
2.5V ≤ VCC ≤ 5.5V
100
—
2.5V ≤ VCC ≤ 5.5V 24FC512
10
TSU:STO Stop condition setup time
4000
—
ns 1.8V ≤ VCC < 2.5V
600
—
2.5V ≤ VCC ≤ 5.5V
250
—
2.5V ≤ VCC ≤ 5.5V 24FC512
11
TSU:WP WP setup time
4000
600
600
12
THD:WP WP hold time
4700
1300
1300
13
TAA
Output valid from clock (Note 2)
—
—
—
14
TBUF Bus free time: Time the bus
4700
must be free before a new trans- 1300
mission can start
500
—
—
—
—
—
—
3500
900
400
—
—
—
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
16
TSP
Input filter spike suppression
—
(SDA and SCL pins)
50
ns All except, 24FC512 (Notes 1 and 3)
17
TWC
Write cycle time (byte or page)
—
5
ms —
18
—
Endurance
1,000,000
—
cycles 25°C (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
© 2005 Microchip Technology Inc.
DS21754G-page 3