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PIC18F6520 Datasheet, PDF (295/380 Pages) Microchip Technology – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6520/8520/6620/8620/6720/8720
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (no carry)
[ label ] RRNCF f [,d [,a]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<n>) â dest<n-1>,
(f<0>) â dest<7>
N, Z
0100 00da ffff ffff
The contents of register âfâ are
rotated one bit to the right. If âdâ is
â0â, the result is placed in W. If âdâ is
â1â, the result is placed back in
register âfâ (default). If âaâ is â0â, the
Access Bank will be selected,
overriding the BSR value. If âaâ is
â1â, then the bank will be selected
as per the BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:
RRNCF REG, 0, 0
Before Instruction
W
REG
=?
= 1101 0111
After Instruction
W
REG
= 1110 1011
= 1101 0111
SETF
Set f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] SETF f [,a]
0 ⤠f ⤠255
a â [0,1]
FFh â f
None
0110 100a ffff ffff
The contents of the specified
register are set to FFh. If âaâ is â0â,
the Access Bank will be selected,
overriding the BSR value. If âaâ is
â1â, then the bank will be selected
as per the BSR value (default).
1
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
0x5A
0xFF
REG,1
 2004 Microchip Technology Inc.
DS39609B-page 293
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