USB84604 Datasheet, PDF (29/61 Pages) Microchip Technology – USB 2.0 HSIC Hi-Speed 4-Port Controller Hub

USB84604
6.2.2 SMBus ACCESSIBLE FUNCTIONS
6.2.2.1 OTP Access over SMBus
The device’s OTP ROM is accessible over SMBus. All OTP parameters can be modified via the SMBus Host. The OTP
can be programmed to operate in Single-Ended, Differential, Redundant, or Differential Redundant mode, depending
on the level of reliability required. The supported commands can be found on our web site at www.microchip.com.
Refer to the product page of the USB84604.
6.2.2.2 Configuration Access over SMBus
The functions that are available over SMBus prior to the hub attaching to the USB host are described in AN 26.18
SMBus Slave Interface for the USB253x/USB3x13/USB46x4 [ 7].
6.2.2.3 Run Time Access over SMBus
There is a limited number of registers that are accessible via the SMBus during run time operation of the device. Refer
to AN 26.18 SMBus Slave Interface for the USB253x/USB3x13/USB46x4 [ 7] for details.
6.3 Device Configuration Straps
Configuration straps are multi-function pins that are driven as outputs during normal operation. During a Power-On
Reset (POR) or an External Chip Reset (RESET_N), these outputs are tri-stated. The high or low state of the signal is
latched following de-assertion of the reset and is used to determine the default configuration of a particular feature. Con-
figuration straps are latched as a result of a Power-On Reset (POR) or a External Chip Reset (RESET_N). Configuration
strap signals are noted in Chapter 3.0 Pin Descriptions on page 8 and are identified by an underlined symbol name. The
following sub-sections detail the various configuration straps.
Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a partic-
ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal
resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden
by the addition of an external resistor.
Note:
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, "Reset and Configuration Strap Timing," on page 48 and Section 9.6.1, "Power-On Config-
uration Strap Valid Timing," on page 47. If configuration straps are not at the correct voltage level prior to
being latched, the device may capture incorrect strap values.
Note: Configuration straps must never be driven as inputs. If required, configuration straps can be augmented,
or overridden with external resistors.
6.3.1 PORT DISABLE (PRT_DIS_Mx/PRT_DIS_Px)
These configuration straps disable the associated USB ports D- and D+ signals, respectively, where “x” is the USB port
number. Both the negative “M” and positive “P” port disable configuration straps for a given USB port must be tied high
at reset to disable the associated port.
TABLE 6-1: PRT_DIS_Mx/PRT_DIS_Px CONFIGURATION DEFINITIONS
PRT_DIS_MX/PRT_DIS_PX
‘0’
‘1’
Definition
Port x D-/D+ signal is enabled (default)
Port x D-/D+ signal is disabled
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DS60001295C-page 29