USB3300 Datasheet, PDF (29/53 Pages) SMSC Corporation – HI SPEED USB HOST OR DEVICE PHY WITH ULPI LOW PIN INTERFACE

USB3300
Once, the USB3300 completes transmitting, the DP/DM lines return to idle and an RXD CMD is returned to the Link so
the inter-packet timers may be updated by linestate.
In the case of Full Speed or Low Speed, once STP is asserted each FS/LS bit transition will generate a RXD CMD since
the bit times are relatively slow.
6.1.8 USB3300 RECEIVER
The USB3300 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects
the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority
and will immediately follow register reads and RXD CMD transfers. Figure 6-7, "ULPI Receive" shows a basic USB
packet received by the USB3300 over the ULPI interface.
FIGURE 6-7:
ULPI RECEIVE
CLK
DATA[7:0]
Idle
Turn
around
Rxd
Cmd
PID
D1
Rxd
Cmd
D2
Turn
around
DIR
STP
NXT
In Figure 6-7, "ULPI Receive" the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR
and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted
and DIR is asserted, the RXD CMD data is transferred to the Link. After the last byte of the USB receive packet is trans-
ferred to the PHY, the linestate will return to idle.
The ULPI full speed receiver operates according to the UTMI/ULPI specification. In the full speed case, the NXT signal
will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXD CMD is
driven on the data bus.
In full speed, the USB3300 will not issue a Rxactive de-assertion in the RXD CMD until the DP/DM linestate transition
to idle. This prevents the Link from violating the two full speed bit times minimum turn around time.
6.1.8.1 Disconnect Detection
A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during
a SOF packet. The USB3300 only looks for a high speed disconnect during the long EOP where the period is long
enough for the disconnect reflection to return to the host PHY. When a high speed disconnect occurs the USB3300 will
return a RXD CMD and set the host disconnect bit in the ULPI interrupt status register (address 13h).
When in FS or LS modes, the Link is expected to handle all disconnect detection.
6.1.9 LOW POWER MODE
Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when
the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the
interface pins, full speed receiver, VBUS comparators, and ID comparator.
 2014-2015 Microchip Technology Inc.
DS00001783B-page 29