DSPIC33FJ256GP710T Datasheet, PDF (29/322 Pages) Microchip Technology – dsPIC33FJXXXGPX06/X08/X10 Data Sheet

dsPIC33FJXXXGPX06/X08/X10
3.5 Arithmetic Logic Unit (ALU)
The dsPIC33FJXXXGPX06/X08/X10 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as Bor-
row and Digit Borrow bits, respectively, for subtraction
operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The
dsPIC33FJXXXGPX06/X08/X10
CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor
division.
3.5.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
1. 16-bit x 16-bit signed
2. 16-bit x 16-bit unsigned
3. 16-bit signed x 5-bit (literal) unsigned
4. 16-bit unsigned x 16-bit unsigned
5. 16-bit unsigned x 5-bit (literal) unsigned
6. 16-bit unsigned x 16-bit signed
7. 8-bit unsigned x 8-bit unsigned
3.5.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
3.6 DSP Engine
The DSP engine consists of a high-speed,
17-bit x 17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJXXXGPX06/X08/X10 is a single-cycle,
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow is
not possible. However, some MCU ALU and DSP engine
resources may be used concurrently by the same
instruction (e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for AccA (SATA).
5. Automatic saturation on/off for AccB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection (ACCSAT).
Table 3-1 provides a summary of DSP instructions. A
block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
A=0
Yes
A = (x – y)²
No
A = A + (x – y)²
No
A = A + (x * y)
Yes
A = A + x²
No
No change in A
Yes
A=x*y
No
A=x²
No
A=–x*y
No
A=A–x*y
Yes
© 2009 Microchip Technology Inc.
DS70286C-page 27