DSPIC30F5011-20I Datasheet, PDF (29/224 Pages) Microchip Technology – dsPIC30F5011/5013 Data Sheet

dsPIC30F5011/5013
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
EA<15> = 0
Data ¹⁶
Space
EA
15
EA<15> = 1
Data Space
0x0000
PSVPAG⁽¹⁾
0x01
8
Program Space
0x8000
Address
23
15
15 Concatenation 23
0x000100
0
0x008000
Upper Half of Data
Space is Mapped
into Program Space
0xFFFF
0x017FFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x01, W0
W0, PSVPAG
0x8000, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
3.2 Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1 DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
© 2006 Microchip Technology Inc.
DS70116F-page 27