ENC624J600-I Datasheet, PDF (28/168 Pages) Microchip Technology – Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface

TABLE 3-7: ENC424J600/624J600 REGISTER FILE SUMMARY
File
Name
8-Bit
16-Bit
Bit 7
Bit 15
Bit 6
Bit 14
High Byte (‘H’ Register)
Bit 5
Bit 4
Bit 3
Bit 13
Bit 12
Bit 11
Bit 2
Bit 10
Bit 1
Bit 9
Bit 0
Bit 8
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Low Byte (‘L’ Register)
Bit 4
Bit 3
Bit 4
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Reset
EUDAST
EUDAND
ESTAT
EIR
ECON1
ETXST
ETXLEN
ERXST
ERXTAIL
ERXHEAD
EDMAST
EDMALEN
EDMADST
EDMACS
ETXSTAT
ETXWIRE
EHT1
EHT2
ETH3
ETH4
EPMM1
EPMM2
EPMM3
EPMM4
EPMCS
ERXFCON
EPMO
MACON1
MACON2
MABBIPG
MAIPG
MACLCON
MAMXFL
Legend:
—
User-Defined Area Start Pointer (EUDAST<14:8>)
User-Defined Area Start Pointer (EUDAST<7:0>)
00, 00
—
User-Defined Area End Pointer (EUDAND<14:8>)
User-Defined Area End Pointer (EUDAND<7:0>)
5F, FF
INT
FCIDLE RXBUSY CLKRDY
r
PHYDPX
r
PHYLNK PKTCNT7 PKTCNT6 PKTCNT5 PKTCNT4 PKTCNT3 PKTCNT2 PKTCNT1 PKTCNT0 00, 00
CRYPTEN MODEXIF HASHIF AESIF
LINKIF
r
r
r
r
PKTIF DMAIF
r
TXIF TXABTIF RXABTIF PCFULIF 0A, 00
MODEXST HASHEN HASHOP HASHLST AESST AESOP1 AESOP0 PKTDEC FCOP1 FCOP0 DMAST DMACPY DMACSSD DMANOCS TXRTS RXEN 00, 00
—
TX Start Address (ETXST<14:8>)
TX Start Address (ETXST<7:0>)
00, 00
—
TX Length (ETXLEN<14:8>)
TX Length (ETXLEN<7:0>)
00, 00
—
RX Buffer Start Address (ERXST<14:8>)
RX Buffer Start Address (ERXST<7:0>)
53, 40
—
RX Tail Pointer (ERXTAIL<14:8>)
RX Tail Pointer (ERXTAIL<7:0>)
5F, FE
—
RX Head Pointer (ERXHEAD<14:8>)
RX Head Pointer (ERXHEAD<7:0>)
53, 40
—
DMA Start Address (EDMAST<14:8>)
DMA Start Address (EDMAST<7:0>)
00, 00
—
DMA Length (EDMALEN<14:8>)
DMA Length (EDMALEN<7:0>)
00, 00
—
DMA Destination Address (EDMADST<14:8>)
DMA Destination Address (EDMADST<7:0>)
00, 00
DMA Checksum, High Byte (EDMACS<15:8>)
DMA Checksum, Low Byte (EDMACS<7:0>)
00, 00
—
—
—
r
r
LATECOL MAXCOL EXDEFER DEFER
r
r
CRCBAD COLCNT3 COLCNT2 COLCNT1 COLCNT0 00, 00
Transmit Byte Count on Wire (including collision bytes), High Byte (ETXWIRE<15:8>)
Transmit Byte Count on Wire (including collision bytes), Low Byte (ETXWIRE<7:0>)
00, 00
Hash Table Filter (EHT1<15:8>)
Hash Table Filter (EHT1<7:0>)
00, 00
Hash Table Filter (EHT2<31:24>)
Hash Table Filter (EHT2<23:16>)
00, 00
Hash Table Filter (EHT3<47:40>)
Hash Table Filter (EHT3<39:32>)
00, 00
Hash Table Filter (EHT4<63:56>)
Hash Table Filter (EHT4<55:48>)
00, 00
Pattern Match Filter Mask (EPMM1<15:8>)
Pattern Match Filter Mask (EPMM1<7:0>)
00, 00
Pattern Match Filter Mask (EPMM2<15:8>)
Pattern Match Filter Mask (EPMM2<7:0>)
00, 00
Pattern Match Filter Mask (EPMM3<15:8>)
Pattern Match Filter Mask (EPMM3<7:0>)
00, 00
Pattern Match Filter Mask (EPMM4<15:8>)
Pattern Match Filter Mask (EPMM4<7:0>)
00, 00
Pattern Match Filter Checksum, High Byte (EPMCS<15:8>)
Pattern Match Filter Checksum, Low Byte (EPMCS<7:0>)
00, 00
HTEN
MPEN
—
NOTPM PMEN3 PMEN2 PMEN1 PMEN0 CRCEEN CRCEN RUNTEEN RUNTEN UCEN NOTMEEN MCEN BCEN 00, 59
Pattern Match Filter Offset, High Byte (EPMO<15:8>)
Pattern Match Filter Offset, Low Byte (EPMO<7:0>)
00, 00
r
r
—
—
r
r
r
r
—
—
—
LOOPBK
r
RXPAUS PASSALL
r
x0, 0D
—
DEFER BPEN NOBKOFF
—
—
r
r
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN
r
FULDPX 40, B2
—
—
—
—
—
—
—
—
—
BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 00, 12
—
r
r
r
r
r
r
r
—
IPG6
IPG5
IPG4
IPG3
IPG2
IPG1
IPG0 0C, 12
—
—
r
r
r
r
r
r
—
—
—
—
MAXRET3 MAXRET2 MAXRET1 MAXRET0 37, 0F
MAC Maximum Frame Length, High Byte (MAMXFL<15:8>)
MAC Maximum Frame Length, Low Byte (MAMXFL<7:0>)
05, EE
— = unimplemented, read as ‘0’; q = unique MAC address or silicon revision nibble; r = reserved bit, do not modify; x = Reset value unknown. Reset values are shown in hexadecimal for each byte.