DSPIC33FJ32GP202_11 Datasheet, PDF (278/284 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
I²C Module
I2C1 Register Map ...................................................... 40
In-Circuit Debugger ........................................................... 189
In-Circuit Emulation........................................................... 183
In-Circuit Serial Programming (ICSP) ....................... 183, 189
Input Capture
Registers ................................................................... 144
Input Change Notification.................................................. 114
Instruction Addressing Modes............................................. 47
File Register Instructions ............................................ 47
Fundamental Modes Supported.................................. 48
MAC Instructions......................................................... 48
MCU Instructions ........................................................ 47
Move and Accumulator Instructions ............................ 48
Other Instructions........................................................ 48
Instruction Set
Overview ................................................................... 194
Summary................................................................... 191
Instruction-Based Power-Saving Modes ........................... 109
Idle ............................................................................ 110
Sleep ......................................................................... 109
Internal RC Oscillator
Use with WDT ........................................................... 187
Internet Address................................................................ 281
Interrupt Control and Status Registers................................ 75
IECx ............................................................................ 75
IFSx............................................................................. 75
INTCON1 .................................................................... 75
INTCON2 .................................................................... 75
IPCx ............................................................................ 75
Interrupt Setup Procedures ................................................. 97
Initialization ................................................................. 97
Interrupt Disable.......................................................... 97
Interrupt Service Routine ............................................ 97
Trap Service Routine .................................................. 97
Interrupt Vector Table (IVT) ................................................ 71
Interrupts Coincident with Power Save Instructions.......... 110
J
JTAG Boundary Scan Interface ........................................ 183
M
Memory Organization.......................................................... 31
Microchip Internet Web Site .............................................. 281
Modulo Addressing ............................................................. 49
Applicability ................................................................. 50
Operation Example ..................................................... 49
Start and End Address ................................................ 49
W Address Register Selection .................................... 49
MPLAB ASM30 Assembler, Linker, Librarian ................... 200
MPLAB Integrated Development Environment Software .. 199
MPLAB PM3 Device Programmer..................................... 202
MPLAB REAL ICE In-Circuit Emulator System................. 201
MPLINK Object Linker/MPLIB Object Librarian ................ 200
N
NVM Module
Register Map............................................................... 46
O
Open-Drain Configuration ................................................. 114
Output Compare................................................................ 145
Registers ................................................................... 147
P
Packaging ......................................................................... 257
Details....................................................................... 259
Marking ............................................................. 257, 258
Peripheral Module Disable (PMD) .................................... 110
Pinout I/O Descriptions (table)............................................ 13
PMD Module
Register Map .............................................................. 46
PORTA
Register Map .............................................................. 45
PORTB
Register Map .............................................................. 45
Power-on Reset (POR)....................................................... 68
Power-Saving Features .................................................... 109
Clock Frequency and Switching ............................... 109
Program Address Space..................................................... 31
Construction ............................................................... 52
Data Access from Program Memory Using
Program Space Visibility..................................... 55
Data Access from Program Memory Using
Table Instructions ............................................... 54
Data Access from, Address Generation ..................... 53
Memory Map............................................................... 31
Table Read Instructions
TBLRDH ............................................................. 54
TBLRDL.............................................................. 54
Visibility Operation ...................................................... 55
Program Memory
Interrupt Vector ........................................................... 32
Organization ............................................................... 32
Reset Vector ............................................................... 32
R
Reader Response............................................................. 282
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 179
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 177
AD1CON1 (ADC1 Control 1) .................................... 173
AD1CON2 (ADC1 Control 2) .................................... 175
AD1CON3 (ADC1 Control 3) .................................... 176
AD1CSSL (ADC1 Input Scan Select Low)................ 181
AD1PCFGL (ADC1 Port Configuration Low) ............ 181
CLKDIV (Clock Divisor) ............................................ 104
CORCON (Core Control) ...................................... 24, 76
I2CxCON (I2Cx Control) ........................................... 157
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 161
I2CxSTAT (I2Cx Status) ........................................... 159
ICxCON (Input Capture x Control)............................ 144
IEC0 (Interrupt Enable Control 0) ................... 84, 86, 87
IFS0 (Interrupt Flag Status 0) ..................................... 80
IFS1 (Interrupt Flag Status 1) ..................................... 82
IFS4 (Interrupt Flag Status 4) ..................................... 83
INTCON1 (Interrupt Control 1).................................... 77
INTCON2 (Interrupt Control 2).................................... 79
INTTREG Interrupt Control and Status Register ........ 96
IPC0 (Interrupt Priority Control 0) ............................... 88
IPC1 (Interrupt Priority Control 1) ............................... 89
IPC16 (Interrupt Priority Control 16) ........................... 95
IPC2 (Interrupt Priority Control 2) ............................... 90
IPC3 (Interrupt Priority Control 3) ............................... 91
IPC4 (Interrupt Priority Control 4) ............................... 92
IPC5 (Interrupt Priority Control 5) ............................... 93
IPC7 (Interrupt Priority Control 7) ............................... 94
NVMCOM (Flash Memory Control)....................... 59, 60
OCxCON (Output Compare x Control) ..................... 147
OSCCON (Oscillator Control) ................................... 102
OSCTUN (FRC Oscillator Tuning)............................ 107
PLLFBD (PLL Feedback Divisor).............................. 106
DS70290G-page 278
© 2011 Microchip Technology Inc.