DSPIC33FJ128MC802-ISP Datasheet, PDF (273/425 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
22.0 10-BIT/12-BIT ANALOG-TO-
DIGITAL CONVERTER (ADC1)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04
and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 16. Analog-to-Digital
Converter (ADC)” (DS70183) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices have up
to 9 ADC input channels.
The AD12B bit (AD1CON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
Note: The ADC module needs to be disabled
before modifying the AD12B bit.
22.1 Key Features
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to nine analog input pins
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only one sample/hold amplifier in the
12-bit configuration, so simultaneous sampling of
multiple channels is not supported.
Depending on the particular device pinout, the ADC
can have up to nine analog input pins, designated AN0
through AN8. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs can be shared with other
analog input pins. The actual number of analog input
pins and external voltage reference input configuration
depends on the specific device.
Block diagrams of the ADC module are shown in
Figure 22-1 and Figure 22-2.
22.2 ADC Initialization
The following configuration steps should be performed.
1. Configure the ADC module:
a) Select port pins as analog inputs
(AD1PCFGH<15:0> or AD1PCFGL<15:0>)
b) Select voltage reference source to match
expected range on analog inputs
(AD1CON2<15:13>)
c) Select the analog conversion clock to
match desired data rate with processor
clock (AD1CON3<7:0>)
d) Determine how many S/H channels is used
(AD1CON2<9:8> and AD1PCFGH<15:0>
or AD1PCFGL<15:0>)
e) Select the appropriate sample/conversion
sequence
(AD1CON1<7:5>
and
AD1CON3<12:8>)
f) Select how conversion results are
presented in the buffer (AD1CON1<9:8>)
g) Turn on ADC module (AD1CON1<15>)
2. Configure ADC interrupt (if required):
a) Clear the AD1IF bit
b) Select ADC interrupt priority
22.3 ADC and DMA
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. ADC1 can trigger a DMA data transfer. If
ADC1 is selected as the DMA IRQ source, a DMA
transfer occurs when the AD1IF bit gets set as a result
of an ADC1 sample conversion sequence.
The SMPI<3:0> bits (AD1CON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
The ADDMABM bit (AD1CON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module
provides an address to the DMA channel that is the
same as the address used for the non-DMA stand-
alone buffer. If the ADDMABM bit is cleared, then DMA
buffers are written in Scatter/Gather mode. The module
provides a scatter/gather address to the DMA channel,
based on the index of the analog input and the size of
the DMA buffer.
© 2009 Microchip Technology Inc.
Preliminary
DS70291D-page 273