DSPIC33FJ128MC802-ISP Datasheet, PDF (18/425 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
TMS
TCK
TDI
TDO
I
ST
No JTAG Test mode select pin.
I
ST
No JTAG test clock input pin.
I
ST
No JTAG test data input pin.
O
—
No JTAG test data output pin.
INDX1
QEA1
QEB1
UPDN1
I
ST
Yes Quadrature Encoder Index1 Pulse input.
I
ST
Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
I
ST
Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
O CMOS Yes Position Up/Down Counter Direction State.
INDX2
QEA2
QEB2
UPDN2
C1RX
C1TX
I
ST
Yes Quadrature Encoder Index2 Pulse input.
I
ST
Yes Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
I
ST
Yes Quadrature Encoder Phase A input in QEI2 mode. Auxiliary Timer
External Clock/Gate input in Timer mode.
O CMOS Yes Position Up/Down Counter Direction State.
I
ST
Yes ECAN1 bus receive pin.
O
—
Yes ECAN1 bus transmit pin.
RTCC
O
—
No Real-Time Clock Alarm Output.
CVREF
O
C1IN-
I
C1IN+
I
C1OUT
O
C2IN-
I
C2IN+
I
C2OUT
O
PMA0
I/O
PMA1
I/O
PMA2 -PMPA10 O
PMBE
O
PMCS1
O
PMD0-PMPD7 I/O
PMRD
O
PMWR
O
ANA
ANA
ANA
—
ANA
ANA
—
TTL/ST
TTL/ST
—
—
—
TTL/ST
—
—
No Comparator Voltage Reference Output.
No Comparator 1 Negative Input.
No Comparator 1 Positive Input.
Yes Comparator 1 Output.
No Comparator 2 Negative Input.
No Comparator 2 Positive Input.
Yes Comparator 2 Output.
No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address (Demultiplexed Master Modes).
No Parallel Master Port Byte Enable Strobe.
No Parallel Master Port Chip Select 1 Strobe.
No Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
No Parallel Master Port Read Strobe.
No Parallel Master Port Write Strobe.
DAC1RN
DAC1RP
DAC1RM
O
—
No DAC1 Negative Output.
O
—
No DAC1 Positive Output.
O
—
No DAC1 Output indicating middle point value (typically 1.65V).
DAC2RN
DAC2RP
DAC2RM
O
—
No DAC2 Negative Output.
O
—
No DAC2 Positive Output.
O
—
No DAC2 Output indicating middle point value (typically 1.65V).
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
DS70291D-page 18
Preliminary
© 2009 Microchip Technology Inc.