PIC12F1840 Datasheet, PDF (261/376 Pages) Microchip Technology – 8-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC12F/LF1840
REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1
R/C/HS-0/0
WCOL
bit 7
R/C/HS-0/0
SSP1OV
R/W-0/0
SSP1EN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
SSP1M<3:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
C = User cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
2:
3:
4:
5:
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSP1BUF register was attempted while the I²C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSP1OV: Receive Overflow Indicator bit⁽¹⁾
In SPI mode:
1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR
is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting
data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSP1BUF register (must be cleared in software).
0 = No overflow
In I²C mode:
1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit
mode (must be cleared in software).
0 = No overflow
SSP1EN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins⁽²⁾
0 = Disables serial port and configures these pins as I/O port pins
In I²C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins⁽³⁾
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I²C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I²C Master mode:
Unused in this mode
SSP1M<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I²C Slave mode, 7-bit address
0111 = I²C Slave mode, 10-bit address
1000 = I²C Master mode, clock = FOSC / (4 * (SSP1ADD+1))⁽⁴⁾
1001 = Reserved
1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))⁽⁵⁾
1011 = I²C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF
register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSP1ADD values of 0, 1 or 2 are not supported for I²C Mode.
SSP1ADD value of ‘0’ is not supported. Use SSP1M = 0000 instead.
 2011 Microchip Technology Inc.
Preliminary
DS41441A-page 261