DSPIC33FJ32MC204T-IPT Datasheet, PDF (259/330 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 32 KB Flash and 2 KB SRAM) with Motor Control and Advanced Analog

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
FIGURE 24-15:
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING
CHARACTERISTICS
SP36
SP10
SP21
SP20
SP35
SP20
SP21
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic⁽¹⁾
Min Typ⁽²⁾ Max Units
Conditions
SP10 TscP
Maximum SCK Frequency
—
—
15 MHz ^{See Note 3}
SP20 TscF
SCKx Output Fall Time
—
—
—
ns See parameter DO32
and Note 4
SP21 TscR
SCKx Output Rise Time
—
—
—
ns See parameter DO31
and Note 4
SP30 TdoF
SDOx Data Output Fall Time
—
—
—
ns See parameter DO32
and Note 4
SP31 TdoR
SDOx Data Output Rise Time
—
—
—
ns See parameter DO31
and Note 4
SP35 TscH2doV, SDOx Data Output Valid after
—
6
20
ns
—
TscL2doV SCKx Edge
SP36 TdiV2scH, SDOx Data Output Setup to
30
—
—
ns
—
TdiV2scL First SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2012 Microchip Technology Inc.
DS70283K-page 259